1、与或非电路
module AOI(a,b,c,d,out);
input a;
input b;
input c;
input d;
output out;
assign out = ~((a&b)|(c&d));
endmodule
![](https://i-blog.csdnimg.cn/blog_migrate/854aeb4b1e6a2db845566bf19982e20b.png)
2、用case 语句描述的4 选1 数据选择器
module mux4_1(a,b,c,d,sel,out);
input a;
input b;
input c;
input d;
input [1:0]sel;
output reg out;
always @(*)
begin
case(sel)
2'b00: out <= a;
2'b01: out <= b;
2'b10: out <= c;
2'b11: out <= d;
default: out <= 0;
endcase
end
endmodule
![](https://i-blog.csdnimg.cn/blog_migrate/bea971700f4f3e762dbf78087de1abf4.png)
3、同步置数、同步清零的计数器
module count(clk,Rst_n,load,data,out);
input clk;
input Rst_n;
input load;
input [7:0]data;
output reg [7:0] out;
always@(posedge clk)
begin
if(!Rst_n)
out <= 8'b0;
else if(!load)
out <= data;
else
out <= out + 1'b1;
end
endmodule
![](https://i-blog.csdnimg.cn/blog_migrate/5e865e92b09d9f6e557792cbde7ffad6.png)