//上升沿,下降沿,双边沿检测
module Detect(
input clk,
input rst_n,
input data,
output pos,
output neg,
output dou_edge
);
reg data_0,data_1;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
data_0 <= 1'b0;
data_1 <= 1'b0;
end
else
begin
data_0 <= data;
data_1 <= data_0;
end
end
assign pos = data_0 & (~data_1);
assign neg = (~data_0) & data_1;
assign dou_edge = data_0 ^ data_1;
endmodule
边沿检测-Verilog
最新推荐文章于 2023-09-17 21:56:34 发布