8位加法器 -- verilog

module addr8(
	input clk,
	input rst_n,
		
	input [7:0] a,
	input [7:0] b,
	input cin,
	input enable,
	
	output reg [7:0] sum,
	output reg cout
);

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		sum <= 8'b0;
		cout <= 1'b0;
	end
	else if(enable)begin
		{cout,sum} <= a+b+cin;
	end
	else begin
		sum <= sum;
		cout <= cout;
	end
end
endmodule