Verilog语言 四位计数器

module exa0519(
Q,clock,clear,rst_n
);
input clock;
input rst_n;
output Q;
output   clear;
wire clock;
wire rst_n;
reg  clear;
//输出变量Q被定义为寄存器类型
reg [3:0]  Q;
always @( negedge rst_n or posedge clock) begin
    if (!rst_n) begin
        Q<=1'b0;
        clear<=1'b0;
    end
    else if (Q==5'b01111)
    begin
        Q<=4'b0;
        clear<=1'b1;
    end
     else if (Q<5'b01111)
    begin
        Q<=Q+4'b1;
        clear<=1'b0;
    end
end
endmodule

module tb();
reg clock;
reg rst_n;
wire clear;
wire   [3:0]Q;
initial begin
    clock=0;
end
always #5 clock=~clock;
initial begin
    rst_n=1'b0;
    #1 rst_n=1'b1;
end
exa0519 uut(
    .clock(clock),
    .clear(clear),
    .rst_n(rst_n),
    .Q(Q)
);
endmodule

仿真结果：