传参实现SVA蕴含后续算子的延迟

传参实现SVA蕴含后续算子的延迟

1、断言以module的形式写在单独的文件内；

module dut_sva(
		input clk,
		input rst_n);
	reg [31:0] num;
	sequence delay_seq(v_delay);
		int delay;
		(1,delay=v_delay) ##0 first_match((1,delay=delay-1) [*0:$] ##0 delay<=0);
	endsequence
	property busy_down;
		@(posedge clk) disable iff(!rst_n) (fell(`DUT_TOP.a) && `DUT_TOP.b == 1 && mode == 0) |-> delay_seq(num) ##0 (`DUT_TOP.busy == 0)
	endproperty
	busy_down:assert property (busy_down) else $error("xxxxx");
endmodule

2、flist内添加段断言文件路径，在harness内将断言bind在DUT顶层上：

bind harness.DUT_TOP dut_sva U_DUT_SVA(
				.clk(harness.dut.clk),
				.rst_n(harness.dt.rst_n)
);