Verilog分频发生器

二分频

module Div_2(rst,clk,f2);
    input rst,clk;
    output f2;
    reg f2;
    reg c2;
    always @(posedge clk or posedge rst)
        begin
            if (rst) begin c2=1'b1;f2=1'b0;end
            else 
                if (c2>1'b0)
                    begin f2=1'b1;c2=c2-1'b1;end
                else 
                    begin f2=1'b0;c2=1'b1;end
        end
endmodule

四分频

module Div_4(rst,clk,f4);
    input rst,clk;
    output f4;
    reg f4;
    reg [1:0] c4;  
    always @(posedge clk or posedge rst)
        begin
            if (rst) begin c4=2'b11;f4=1'b0;end
            else 
                if (c4>=2'b10)
                    begin f4=1'b1;c4=c4-1'b1;end
                else if (c4!=2'b00)
                    begin f4=1'b0;c4=c4-1'b1;end
                else 
                    c4=2'b11;
        end
endmodule

---

三分频

module Div_3(rst,clk,f3);
    input rst,clk;
    output f3;
    reg f3a,f3b;
    reg [1:0] c3a,c3b;
    always @(posedge clk or posedge rst)
        if (rst) 
            begin c3a=2'b11;f3a=1'b0;end
        else 
            if (c3a>2'b10) 
                begin f3a=1'b1;c3a=c3a-1'b1;end
            else if (c3a>2'b01) 
                begin f3a=1'b0;c3a=c3a-1'b1;end
            else 
                c3a=2'b11;
    always @(negedge clk or posedge rst)
        if (rst) 
            begin c3b=2'b11;f3b=1'b0;end
        else 
            if (c3b>2'b10) 
                begin f3b=1'b1;c3b=c3b-1'b1;end
            else if (c3b>2'b01) 
                begin f3b=1'b0;c3b=c3b-1'b1;end
            else 
                c3b=2'b11;
    assign f3=f3a|f3b;
endmodule

五分频

module Div_5(rst,clk,f5);
    input rst,clk;
    output f5;
    reg f5a,f5b;
    reg [2:0] c5a,c5b;
    always @(posedge clk or posedge rst)
        if (rst) 
            begin c5a=3'b101;f5a=1'b0;end
        else 
            if (c5a>3'b011) 
                begin f5a=1'b1;c5a=c5a-1'b1;end
            else if (c5a>3'b001)
                begin f5a=1'b0;c5a=c5a-1'b1;end
            else 
                c5a=3'b101;
    always @(negedge clk or posedge rst)
        if (rst) 
            begin c5b=3'b101;f5b=1'b0;end
        else 
            if (c5b>3'b011)
                begin f5b=1'b1;c5b=c5b-1'b1;end
            else if (c5b>3'b001) 
                begin f5b=1'b0;c5b=c5b-1'b1;end
            else 
                c5b=3'b101;
    assign f5=f5a|f5b; 
endmodule