vivado入门：bug解决记录

项目场景：

今天在初学vivado综合时遇到了几个小问题，先简单记录一下，有时间再详细补充：

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问题描述及解决方案：

问题一：在编写过程语句时，数值的表示方式错误
原本想表示十进制数100，在找bug过程中以为这儿有问题，误改成了3’d100。这种表述错误在于100（十进制）并不是三位，而是至少用7位二进制数来表示，也就是说，这里的3’表示是该数据的二进制位数（3’d100的写法显然就错了，直接100就可以）。

问题二：编写vivado设计文件时，变量初始化方式错误
在模块输入输出定义的地方赋了初值，这种方式是错误的。以为题目中没有要求，就没写input rst_n复位端口，但实际上复位端口起到的是初始化变量的重要作用，在仿真乃至电路功能实现上十分重要。

问题三：没理解清vivado几种仿真类型的区别
其实行为级仿真（behavior simulation）的结果并不符合预期，但后仿和预期结果相像，没理解清几种仿真类型的区别就盲目进行后仿，导致找不清错误在哪。
vivado五种仿真类型可参考这篇博客。

问题四：生成bit流操作顺序不对（对vivado界面功能不够熟悉）
报错信息：

[DRC NSTD-1] Unspecified I/O Standard: 102 out of 102 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_ch1[23:0], dout_ch2[23:0], dout_ch3[23:0], dout_ch4[23:0], clk, dout_valid_ch1, dout_valid_ch2, dout_valid_ch3, dout_valid_ch4, and rstn.

[DRC UCIO-1] Unconstrained Logical Port: 102 out of 102 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_ch1[23:0], dout_ch2[23:0], dout_ch3[23:0], dout_ch4[23:0], clk, dout_valid_ch1, dout_valid_ch2, dout_valid_ch3, dout_valid_ch4, and rstn.

具体遇到的错误参见这篇博客，注意有的博客给出解决方法是添加几行代码，但那其实只是忽略这个问题，并没有实际解决。
而我的错误和以上都不同，为了节省时间，我在生成bit流时选择了No，实际上这样会导致生成比特流还是基于之前综合的电路，之前的电路我忘记给一个管脚加约束了，显然是不对的。