Quartus II仿真出现问题Error: can‘t read “FileWatch(fileName)“: no such element in array

Determining the location of the ModelSim executable…

Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off f_adder -c f_adder --vector_source=“C:/intelFPGA_lite/test/f_adder/Waveform.vwf” --testbench_file=“C:/intelFPGA_lite/test/f_adder/simulation/qsim/Waveform.vwf.vht”

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright © 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation’s design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Oct 16 18:54:33 2021
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off f_adder -c f_adder --vector_source=C:/intelFPGA_lite/test/f_adder/Waveform.vwf --testbench_file=C:/intelFPGA_lite/test/f_adder/simulation/qsim/Waveform.vwf.vht
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully.

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=“C:/intelFPGA_lite/test/f_adder/simulation/qsim/” f_adder -c f_adder

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright © 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation’s design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Oct 16 18:54:33 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/intelFPGA_lite/test/f_adder/simulation/qsim/ f_adder -c f_adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file f_adder.vho in folder “C:/intelFPGA_lite/test/f_adder/simulation/qsim//” for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4635 megabytes
Info: Processing ended: Sat Oct 16 18:54:34 2021
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

Completed successfully.

**** Generating the ModelSim .do script ****

C:/intelFPGA_lite/test/f_adder/simulation/qsim/f_adder.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

c:/intelfpga_lite/20.1/modelsim_ase/win32aloem//vsim -c -do f_adder.do

Reading pref.tcl

# 2020.1

# do f_adder.do
# ** Warning: (vlib-34) Library already exists at “work”.

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:54:35 on Oct 16,2021
# vcom -work work f_adder.vho
# – Loading package STANDARD
# – Loading package TEXTIO
# – Loading package std_logic_1164
# – Loading package VITAL_Timing
# – Loading package VITAL_Primitives
# – Loading package cyclone10lp_atom_pack
# – Loading package cyclone10lp_components
# – Compiling entity hard_block
# – Compiling architecture structure of hard_block
# – Compiling entity f_adder
# – Compiling architecture structure of f_adder
# End time: 18:54:35 on Oct 16,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:54:35 on Oct 16,2021
# vcom -work work Waveform.vwf.vht
# – Loading package STANDARD
# – Loading package TEXTIO
# – Loading package std_logic_1164
# – Compiling entity f_adder_vhd_vec_tst
# – Compiling architecture f_adder_arch of f_adder_vhd_vec_tst
# End time: 18:54:35 on Oct 16,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# Error loading design
Error loading design

Error: can’t read “FileWatch(fileName)”: no such element in array

Error.

解决问题的办法

点进去，选择simulation setting, 移除-novopt。然后就能运行了。
也有可能的解决办法请访问
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