questasim仿真命令-1

# //  Questa Sim
# //  Version 10.7c win32 Aug 18 2018
# //
# //  Copyright 1991-2018 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do run_sys_top.do
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1".  Locker is JC@WTT.
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt2".  Locker is JC@WTT.
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim vmap 10.7c Lib Mapping Utility 2018.08 Aug 18 2018
# vmap work work 
# Modifying modelsim.ini
# QuestaSim vlog 10.7c Compiler 2018.08 Aug 18 2018
# Start time: 10:00:02 on Aug 03,2023
# vlog -reportprogress 300 -f ./filelist.f 
# -- Compiling module sys_top_tb
# -- Compiling module switch_ctrl
# -- Compiling module clk_gen
# -- Compiling module rst_gen
# -- Compiling module mult_lpm_mult_181_sg3i7zi
# -- Compiling module mult
# -- Compiling module lpm_mul
# -- Compiling module lpm_multb
# -- Compiling module altfp_mul_altfp_mult_u3o
# -- Compiling module altfp_mul
# -- Compiling module altfp_divde_altfp_div_pst_01f
# -- Compiling module altfp_divde_altfp_div_dkh
# -- Compiling module altfp_divde
# -- Compiling module fp_function
# 
# Top level modules:
# 	sys_top_tb
# 	mult
# 	altfp_mul
# End time: 10:00:03 on Aug 03,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# QuestaSim vcom 10.7c Compiler 2018.08 Aug 18 2018
# Start time: 10:00:03 on Aug 03,2023
# vcom -reportprogress 300 -work ../../src/ip/fp_function/fp_function/fp_function_0002.vhd 
# Usage: vcom [options] files
# Options:
#   -help              Print this message
#   -version           Print the version of the compiler
#   -32                Run in 32-bit mode
#   -64                Run in 64-bit mode
#   -work <path>       Specify library WORK
#   -fatal <msgNumber>[,<msgNumber>...]
#                      Report the listed messages as fatal
#   -error <msgNumber>[,<msgNumber>...]
#                      Report the listed messages as errors
#   -warning <msgNumber>[,<msgNumber>...]
#                      Report the listed messages as warnings
#   -warning error     Report all warnings as errors
#   -note <msgNumber>[,<msgNumber>...]
#                      Report the listed message as notes
#   -suppress <msgNumber/msgGroup>[,<msgNumber/msgGroup>...]
#                      Suppress the listed messages using number or group.
#                      Valid <msgGroup> are All, GroupNote, GroupWarning, GroupFLI, GroupPLI, 
#                      GroupSDF, GroupVCD, GroupVital, GroupWLF, GroupTCHK, GroupPA, GroupLRM
#   -msglimit [all,|none,][-|+]<msgNumber>[,[-|+]<msgNumber>...]
#                      Limit the reporting of listed messages to default count
#   -msglimit [error|warning]
#                      Limit the total number of errors/warnings to default count
#   -msglimitcount <limit_value> -msglimit [all,|none,][-|+]<msgNumber>[,[-|+]<msgNumber>...]
#                      Limit the reporting of listed messages to user defined count
#   -msglimitcount <limit_value> -msglimit [error|warning]
#                      Limit the total number of errors/warnings to user defined count
#   -msgsingleline     Display the messages in a single line.
#   -svfilesuffix=<extension>[,<extension>...]
#                      filename extensions for SystemVerilog code
#   -vamsfilesuffix=<extension>[,<extension>...]
#                      filename extensions for Verilog-AMS code
#   -87                Enable support for VHDL 1076-1987
#   -93                Enable support for VHDL 1076-1993
#   -2002              Enable support for VHDL 1076-2002
#   -2008              Enable support for VHDL 1076-2008
#                      Refer to the technote docs/technotes/vhdl2008.note
#                      for a list of the currently supported 2008 features.
#   -allowProtectedBeforeBody
#                      Allow a variable of protected type to be created prior
#                      to declaring the body
#   -ams99             Enable support for VHDL 1076.1-1999
#   -ams07             Enable support for VHDL 1076.1-2007
#   -addpragmaprefix <prefix>
#                      Enable recognition of synthesis and coverage pragmas with
#                      a user specified prefix.
#   -check_synthesis   Check for compliance to some synthesis rules
#   --------  Access Control and Debug Options  --------
#       These options help maximize simulation performance while retaining access
#       to objects of interest. The effect of this option is limited only to
#       those design units being compiled in the current vcom session.
#   +acc[=<spec>]
#                      <spec> consists of the following letter code:
#                         v (variables, constants, and aliases
#   -assertdebug       Allow to debug SVA/PSL objects, with vsim -assertdebug
#   -fsmdebug          Allow finite state machine recognition and debugging
#   -floatgenerics     Don't lock down generic values during optimization.
#                      This enables use of the vsim -g/G options on the affected
#                      generics.
#   --------
#   -createlib[=compress]
#                      Create libraries that do not exist.
#                      The =compress modifier creates compressed libraries.
#   -nocreatelib       Do not create libraries that do not exist.
#   -coverclkoptbuiltins, -nocoverclkoptbuiltins
#                      Enable or disable clkOpt optimization builtins for code coverage.
#   -bindAtCompile     Perform default binding when compiling the design
#   -bindAtLoad        Perform default binding when the design is loaded (the default)
#   -amsstd            Add VHDL-AMS declarations to package STANDARD
#   -noamsstd          Do not add VHDL-AMS declarations to package STANDARD
#   -ignoreStandardRealVector Ignore the VHDL-2008 declaration of REAL_VECTOR in package STANDARD
#   -nocoversub        Ignore VHDL subprograms for code coverage
#   -coversub          Include VHDL subprograms for code coverage
#   -coverrespecthandl  Inform code coverage optimizations to look for H and L signal values
#   -nocoverrespecthandl  Inform code coverage optimizations to ignore H and L signal values
#   -separateConfigLibrary  Allows VHDL configuration decls in different library from corresponding entity
#   +cover[=<spec>]
#                      <spec> is used to enable code coverage metrics for certain
#                      kinds of constructs.
#                      <spec> consists of one or more of the following letter codes:
#                         s (statement)
#                         b (branch)
#                         c (condition)
#                         e (expression)
#                         f (finite state machine)
#                         t (toggle)
#                         x (extended toggle)
#                      If no <spec> characters are given, sbceft is the default.
#   -coverenhanced     Enables functionality which may change the appearance or content of coverage
#                      metrics. A detailed list of these changes can be found by searching in the
#                      release notes for 'coverenhanced'. This option only takes meaningful effect in
#                      letter releases (e.g. 10.2b). It has no effect in initial major releases (e.g. 10.2).
#   -coveropt <i>      Specify a digit for code coverage optimization level: 1 through 4.
#   -coverexcludedefault Automatically exclude case default clauses.
#   -coverfec          Enable Focused Expression Coverage analysis for conditions and expressions.
#   -nocoverfec        Disable Focused Expression Coverage analysis for conditions and expressions.
#   -coverrec          Enable Rapid Expression Coverage mode of FEC for conditions and expressions.
#   -nocoverrec        Disable Rapid Expression Coverage mode of FEC for conditions and expressions.
#   -coverudp          Enable UDP Coverage analysis for conditions and expressions.
#   -nocoverudp        Disable UDP Coverage analysis for conditions and expressions.
#   -nocovershort      Disable short circuiting of expressions/condition when coverage is enabled.
#   -coverexpandrdpfx  Bit-blast multi-bit operands of reduction prefix expressions for expression/condition coverage.
#   -nocoverexpandrdpfx Don't bit-blast multi-bit operands of reduction prefix expressions for expression/condition coverage.
#   -nocoverexcludedefault Don't automatically exclude case default clauses.
#   -constimmedassert  Show constant immediate assertions in GUI/UCDB/reports etc.
#   -togglecountlimit n Quit collecting toggle info after count n is reached.
#   -togglewidthlimit n Don't collect toggle data on reg's or arrays wider than n.
#   -extendedtogglemode [1|2|3]
#                      Change the level of support for extended toggles.
#                      The levels of support are:
#                      1 - 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z')
#                      2 - 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'
#                      3 - 0L->1H & 1H->0L & all 'Z' transitions
#   -toggleportsonly   Enable toggle statistics collection only for ports.
#   -maxudprows n      Max number of rows allowed in UDP tables for code coverage.
#   -maxfecrows n      Max number of input patterns allowed in FEC table for code coverage.
#   -fecudpeffort n    Limit the size of expressions and conditions considered for expr/cond coverage.
#                      Levels supported are:
#                      1 - (low) Only small expressions and conditions considered for coverage.
#                      2 - (medium) Bigger expressions and conditions considered for coverage.
#                      3 - (high) Very large expressions and conditions considered for coverage.
#   -coverreportcancelled Report coverage items that have been optimized away.
#   -coverdeglitch <period> Report only the last execution of non-clocked processes/continuous assignments
#                      within time greater than <period>, where <period> is 0 or
#                      a time string with units
#   -autoorder         [Experimental feature] Compiler automatically reorders compilation of designs according to dependences.
#   -noautoorderrefresh Omit the final compilation step of -autoorder.
#                      Execute the final compilation step later with -refresh_marked.
#   -autoorderquiet    Do not issue a compilation report in the initial compilation step
#                      when performing -autoorder.
#   -autoorderrefreshquiet Do not issue a compilation report after the final compilation step
#                      when performing -autoorder.
#   -debugVA           Print VITAL cell optimization information
#   -defercheck        Defer all compile-time range checking on constant index and
#                      slice expressions until run time
#   -explicit          Resolve resolution conflicts in favor of explicit functions
#   -deferSubpgmCheck  Defer compile-time range checking on constant index and
#                      slice expressions in subprograms until run time
#   -f <filename>      Specify a file containing more command line arguments
#   -F <filename>      Specify a file containing more command line arguments. Prefixes relative
#                      file names within the arguments file with the absolute path of arguments file,
#                      if lookup with relative path fails.
#   -outf <filename>   Specify a file to save the final list of options after recursively expanding
#                      all -f, -file and -F files.
#   -force_refresh     Force a refresh of the library image from .dat file(s)
#                      even if there are dependency errors
#   -optionset <optionset_name>
#                      Calls an option set in modelsim.ini.
#   -nofsmresettrans   Disable recognition of implicit asynchronous reset transitions for FSMs
#   -fsmresettrans     Enable recognition of implicit asynchronous reset transitions for FSMs
#   -nofsmsingle       Disable recognition FSMs having single bit current state variable
#   -fsmsingle         Enable recognition FSMs having single bit current state variable
#   -fsmimplicittrans  Enable recognition of implicit transitions in FSMs
#   -nofsmimplicittrans Disable recognition of implicit transitions in FSMs
#   -fsmmultitrans     Enable recognition of Multi-state transitions in FSMs
#   -fsmverbose [b|t|w]
#                      Provides information about FSMs recognized, including state reachability analysis.
#                      There are three detail levels that can be set with this option.
#                         b (displays only basic information)
#                         t (displays a transition table in addition to the basic information)
#                         w (displays any warning messages in addition to the basic information)
#                      If no character is specified, btw is the default.
#   -gen_xml <entity> <output>
#                      Output (into a file) the interface definition of the
#                      specified design unit in XML format
#   -gen_xmlstruct <entity> <output>
#                      Similar to -gen_xml, but also output the structural definition
#                      of the specified design unit in XML format
#   -ignoredefaultbinding
#                      Do not generate a default binding during compilation
#   -ignorevitalerrors Ignore VITAL compliance errors
#   -ignorepragmaprefix <prefix>
#                      Ignore synthesis and coverage pragmas with specified prefix
#   -initoutcompositeparam
#                      Initialize array and record mode OUT parameters of subprograms
#   -noinitoutcompositeparam
#                      Do not initialize array and record mode OUT parameters of subprograms
#   -just eapbcx       Compile only selected design unit kinds
#                      (e=entity, a=arch, p=package, b=body, c=config, x=context)
#   -l <filename>      Write compilation log to <filename>
#   -line <lineNum>    Specify a starting line number
#   -lint              Perform lint-style checks
#   -modelsimini <modelsim.ini>
#                      Specify path to the modelsim.ini file
#   -no1164            Disable optimization for the std_logic_1164 package (same as "-noaccel std_logic_1164")
#   -noaccel <pname>   Disable optimization for the specified package
#   -nocasestaticerror Suppress case statement non-static choice warning
#   -nofprangecheck    Disables range check for floating point only
#   -noFunctionInline  Turns off subprogram inlining
#   -nonstddriverinit  Match pre-5.7c behavior for driver initialization
#   -lower             Save all identifiers as lower case names
#   -preserve          Keep case of identifiers, does not make VHDL case sensitive
#   -oldconfigvis      Use pre-10.0 non LRM-compilant visibility for use clauses in configurations
#   -lrmconfigvis      Use LRM-compliant visibility for use clause in configurations
#   -reorderDeclElab   Enable declaration reordering during elaboration to resolve function calls that are used before defined
#   -nocheck           Disable run-time range and index checks
#   -nodebug[=ports][=pli][=ports+pli]
#                      Do not put symbolic debugging information into the library
#   -nodbgsym
#                      Do not generate symbols debugging database
#   -smartdbgsym
#                      Generate symbols debugging database for only some special cases
#   -noDeferSubpgmCheck
#                      Perform compile-time range checking on constant index and
#                      slice expressions in subprograms at compile-time
#   -noindexcheck      Disable run-time index checks
#   -nologo            Disable startup banner
#   -[w]prof=<filename> Enables CPU (-prof) or WALL (-wprof) time based profiling
#                       and saves the profile data to the given filename.
#   -proftick=<integer> Set the time interval between the profile data collection.
#                       Default value is 10.
#   -noothersstaticerror Suppress array aggregate non-static OTHERS choice warning
#   -nopsl             Disable embedded PSL language parsing
#   -norangecheck      Disable run-time range checks
#   -novital           Disable all VITAL optimizations
#   -novitalcheck      Disable VITAL Level 1 compliance checking and optimizations
#   -novopt            Do not run the "vopt" compiler before simulation
#   -nowarn <number>   Disable specified category of warning messages; verror 1907 to see them
#   -noconstimmedassert  Do not show constant immediate assertions in GUI/UCDB/reports etc.
#   -O0                Disable optimizations
#   -O1                Enable some optimizations
#   -O4                Enable most optimizations (default)
#   -O5                Enable additional compiler optimizations
#   -pedanticerrors    Enforce strict language checks
#   -performdefaultbinding
#                      Enable default binding when it has been disabled with the
#                      RequireConfigForAllDefaultBinding modelsim.ini variable
#   -permissive        Relax some language error checks to warnings.
#   +protect[=<file>]  *DEPRECATED* Enable protection/encryption-related compiler directives
#   -pslext            Enable PSL LTL/Universal operators
#   -pslfile <file>    Compile and bind PSL vunits specified by <file>
#   -quiet             Disable 'Loading' messages
#   -rangecheck        Enable run-time range checks
#   -refresh           Refresh the library image from .dat file(s)
#   -refresh_marked    Refresh only design units marked following compilation with
#                      -autoorder along with -noautoorderrefresh.
#   -s                 Do not load package std.standard
#   -skipsynthoffregion Ignore all constructs within synthesis_off or translate_off pragma regions.
#   -skip eapbcx       Compile all but selected design unit kinds
#                      (e=entity, a=arch, p=package, b=body, c=config, x=context)
#   -source            Print the source line with error messages
#   -stats[=[+-]<args>] Enables compiler statistics
#                      <args> are all,none,time,cmd,msg,perf,verbose,list,kb
#   -vitalmemorycheck  Enable VITAL Level 1 Memory model compliance checking
#   -mixedsvvh [b | l | r] [i] [pc]
#                      Facilitates using a VHDL package at the SV-VHDL mixed-language boundary.
#                         b  - treat scalars/vectors in the package as bit
#                         l  - treat scalars/vectors in the package as logic
#                         r  - treat scalars/vectors in the package as reg
#                         i  - ignore range specified with VHDL integer types
#                         pc - preserve case of all identifiers
#   -vopt              Run the "vopt" compiler before simulation
#   -vmake             Collects complete list of command line args for use by vmake.
#   -showsubprograms   Show VHDL subprogram scopes in GUI windows (e.g. Structure) and CLI commands (e.g. show).
#   -noshowsubprograms Don't show VHDL subprogram scopes in GUI windows (e.g. Structure) and CLI commands (e.g. show).(Default on)