verilog全加器和四位加法器

1.基于原理图设计半加器以及全加器以及四位加法器

半加器：

保存为half_addr.bsf之后，可以在该项目中添加半加器

全加器：

通过RTL-Viewer查看半加器和全加器



添加全加器到项目
在process里面先后执行start fitter 和start time analyzer

生成testbench模板

修改testbench文件：

// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "03/06/2023 19:31:56"
                                                                                
// Verilog Test Bench template for design : full_adder
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ps
module full_addr_vlg_tst();
// constants                                           
// general purpose registers

// test vector input registers
reg a;
reg eachvec;
reg b;
reg cin;
// wires                                               
wire cout;
wire sum;

// assign statements (if any)                          
full_addr i1 (
// port map - connection between master ports and signals/registers   
	.a(a),
	.b(b),
	.cin(cin),
	.cout(cout),
	.sum(sum)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
 a=0;b=0;
 cin=0;
 #100 a=0;b=0;cin=1;
 #100 a=1;b=0;cin=1; 
 #100 a=0;b=1;cin=1;    
 #100 a=1;b=1;cin=1;     
 #100 a=1;b=0;cin=0;  
 #100 a=0;b=1;cin=0;                                            
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event