1.基于原理图设计半加器以及全加器以及四位加法器
半加器：
保存为half_addr.bsf之后，可以在该项目中添加半加器
全加器：
通过RTL-Viewer查看半加器和全加器
添加全加器到项目
在process里面先后执行start fitter 和start time analyzer
生成testbench模板
修改testbench文件：
// Copyright (C) 2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "03/06/2023 19:31:56"
// Verilog Test Bench template for design : full_adder
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ns/ 1 ps
module full_addr_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg a;
reg eachvec;
reg b;
reg cin;
// wires
wire cout;
wire sum;
// assign statements (if any)
full_addr i1 (
// port map - connection between master ports and signals/registers
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.sum(sum)
);
initial
begin
// code that executes only once
// insert code here --> begin
a=0;b=0;
cin=0;
#100 a=0;b=0;cin=1;
#100 a=1;b=0;cin=1;
#100 a=0;b=1;cin=1;
#100 a=1;b=1;cin=1;
#100 a=1;b=0;cin=0;
#100 a=0;b=1;cin=0;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
添加到项目
注意在联合modelsim时让generate functinal simulation netlist值为on
zhi
执行start eda netlist writer
选择Gate Level Simulation进行modelsim联合仿真：
执行tcl绑定引脚：
将fpga连接电脑，安装usb-blaster驱动
注意选择驱动安装目录一般是在C:\intelFPGA\18.0\quartus\drivers\usb-blaster
点击programmer进入烧录，记得打开开发板的sw19按钮！
hardwaresetup选择usb-balster,start开始烧录
烧录完成后改变对应的引脚观察输出，本次用到的DE2-115的引脚配置
基于全加器我们马上就可以构建四位全加器：
修改testbench文件如下：
// Copyright (C) 2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "03/20/2023 22:24:30"
// Verilog Test Bench template for design : 4addr
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ns/ 1 ps
module addr_4_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg a1;
reg a2;
reg a3;
reg a4;
reg b1;
reg b2;
reg b3;
reg b4;
reg cin;
// wires
wire out;
wire s1;
wire s2;
wire s3;
wire s4;
// assign statements (if any)
addr_4 i1 (
// port map - connection between master ports and signals/registers
.a1(a1),
.a2(a2),
.a3(a3),
.a4(a4),
.b1(b1),
.b2(b2),
.b3(b3),
.b4(b4),
.cin(cin),
.out(out),
.s1(s1),
.s2(s2),
.s3(s3),
.s4(s4)
);
initial
begin
// code that executes only once
// insert code here --> begin
a4=0;b4=0;a3=0;b3=0;a2=0;b2=0;a1=0;b1=0;cin=0;
#100 a4=0;b4=0;a3=0;b3=0;a2=0;b2=0;a1=1;b1=0;cin=0;
#100 a4=0;b4=0;a3=0;b3=0;a2=0;b2=0;a1=0;b1=1;cin=0;
#100 a4=0;b4=0;a3=0;b3=0;a2=0;b2=0;a1=1;b1=1;cin=0;
#100 a4=0;b4=0;a3=0;b3=0;a2=0;b2=1;a1=0;b1=1;cin=0;
#100 a4=0;b4=0;a3=0;b3=0;a2=1;b2=0;a1=0;b1=1;cin=1;
#100 a4=0;b4=0;a3=0;b3=0;a2=1;b2=1;a1=0;b1=1;cin=1;
#100 a4=0;b4=0;a3=0;b3=1;a2=0;b2=1;a1=0;b1=1;cin=1;
#100 a4=0;b4=0;a3=1;b3=0;a2=1;b2=0;a1=0;b1=1;cin=1;
#100 a4=0;b4=0;a3=1;b3=1;a2=1;b2=1;a1=0;b1=1;cin=1;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
modelsim联合仿真结果：
2.使用verilog编写全加器和四位加法器
v_addr.v代码：
module v_addr(
//输入信号，ain表示被加数，bin表示加数，cin表示低位向高位的进位
input ain,bin,cin,
//输出信号,cout表示向高位的进位，sum表示本位的相加和
output reg cout,sum
);
reg s1,s2,s3;
always @(ain or bin or cin) begin
sum=(ain^bin)^cin;//本位和输出表达式
s1=ain&cin;
s2=bin&cin;
s3=ain&bin;
cout=(s1|s2)|s3;//高位进位输出表达式
end
endmodule
v_addr_tb.v代码：
`timescale 1 ns/ 1 ps
module v_addr_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg ain;
reg bin;
reg cin;
// wires
wire cout;
wire sum;
// assign statements (if any)
v_addr i1 (
// port map - connection between master ports and signals/registers
.ain(ain),
.bin(bin),
.cin(cin),
.cout(cout),
.sum(sum)
);
initial
begin
// code that executes only once
// insert code here --> begin
ain=0;bin=0;
cin=0;
#100 ain=0;bin=0;cin=1;
#100 ain=1;bin=0;cin=1;
#100 ain=0;bin=1;cin=1;
#100 ain=1;bin=1;cin=1;
#100 ain=1;bin=0;cin=0;
#100 ain=0;bin=1;cin=0;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
仿真波形：
四位加法器代码：
module v4_addr(a,b,cin,cout,dout);
input [3:0] a,b; //a，b为4位输入
input cin; //cin为进位输入
output cout;
output [3:0] dout;
assign {cout,dout} = a+b+cin; //a+b+cin 加法操作
//使用拼接运算符将cout、dout拼接，dout取结果中的低四位
endmodule
验证代码：
`timescale 10 ns/ 1 ps
module v4_addr_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg [3:0] a;
reg [3:0] b;
reg cin;
// wires
wire cout;
wire [3:0] dout;
// assign statements (if any)
v4_addr i1 (
// port map - connection between master ports and signals/registers
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.dout(dout)
);
initial
begin
// code that executes only once
// insert code here --> begin
a=4'b0000;b=4'b0001;cin=4'b0000;
#100 a=4'b0001;b=4'b0001;cin=4'b0000;
#100 a=4'b0011;b=4'b0010;cin=4'b0000;
#100 a=4'b0011;b=4'b0100;cin=4'b0001;
#100 a=4'b0100;b=4'b0111;cin=4'b0000;
#100 a=4'b1111;b=4'b0101;cin=4'b0000;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
仿真波形：
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