Compile Error in Vivado

Background INFO

I’m writing a 2-to-1 multiplexer, which should simple and easy to coding.

And below is the source.

module mux2(input sel, input in[0], input in[1], output out);
    assign out = sel? in[1] : in[0];
endmodule

As usual, after writing this code, I write a testbench for the short module aims at checking everything is Okay. However, when I clik the botton SIMULATION, an error happened accidently.

ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'D:/PTC_Vivado/mux2/mux2.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

Process of takling

Commonly, we copy these error INFO, and search in Google

Um, too many “maybe” solutions. Luckily, a bloger named 馬鹿吖 show us a meaningful method: CHECK YOUR LOG!

xvlog

Infact, the Xilinx company has design a significant approach for user to check the error in simulation. By default, the “xvlog” is in the subproject of your design file. And here is my address

"D:\PTC_Vivado\mux2\mux2.sim\sim_1\behav\xsim\xvlog.log"

And in this log file, I find some best answer:
“parameter should not have an array!”
Ohh, so design in before, I had create a array that should be useful while assignment in my opinion.

Outcome

So, I delete the array in parameter, and then simulation is correct!