vivado FIR核报错

最新推荐文章于 2024-07-03 19:35:12 发布

zjemail2120110819

最新推荐文章于 2024-07-03 19:35:12 发布

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文章标签： fpga开发

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# -- Loading package STANDARD
# ** Error: (vcom-11) Could not find unisim.vcomponents.
# ** Error (suppressible): ../../../../project_1.ip_user_files/ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd(73): (vcom-1195) Cannot find expanded name "unisim.vcomponents".
# ** Error: ../../../../project_1.ip_user_files/ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd(73): in protected region
# ** Note: ../../../../project_1.ip_user_files/ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd(73): VHDL Compiler exiting
# End time: 23:02:45 on Aug 20,2022, Elapsed time: 0:00:00
# Errors: 3, Warnings: 1
# child process exited abnormally
# Error in macro ./fir_tb_compile.do line 30

上面报错一堆，谁能告诉我上面错误，到xilinx官网，问了。也没问出来什么原因。下面的地方，必须选择verilog. 如果选mixed,就报错。没法仿真了。也是无语了。