乒乓操作（使用两个读写时钟不同的双口 RAM 实现低速模块处理高速数据的乒乓操作）

顶层设计来自野火哥出品的FPGA Verilog开发实战指南（入门良心书籍）

代码是自己手码的

module  pingpang
(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n     


);

wire            clk_50m        ;
wire            clk_25m        ;
wire            rst_n          ;
wire    [15:0]  ram1_rd_data   ;
wire    [15:0]  ram2_rd_data   ;
wire            data_en        ;
wire    [7:0]   data_in        ;                    
wire            ram1_wr_en     ;
wire    [6:0]   ram1_wr_addr   ;
wire    [7:0]   ram1_wr_data   ;
wire            ram1_rd_en     ;
wire    [6:0]   ram1_rd_addr   ;
wire    [15:0]  data_out       ;
wire            ram2_wr_en     ;
wire    [6:0]   ram2_wr_addr   ;
wire    [7:0]   ram2_wr_data   ;
wire            ram2_rd_en     ;
wire    [6:0]   ram2_rd_addr   ;
wire            locked         ;




assign  rst_n = ((locked)&&(sys_rst_n));

ram_ctrl    ram_ctrl_inst
(
    .clk_50m      (clk_50m)      ,
    .clk_25m      (clk_25m)      ,
    .rst_n        (rst_n)      ,
    .ram1_rd_data (ram1_rd_data)      ,
    .ram2_rd_data (ram2_rd_data)      ,
    .data_en      (data_en)      ,
    .data_in      (data_in)          ,
    
    .ram1_wr_en   (ram1_wr_en)     ,
    .ram1_wr_addr (ram1_wr_addr)     ,
    .ram1_wr_data (ram1_wr_data)     ,
    .ram1_rd_en   (ram1_rd_en)     ,
    .ram1_rd_addr (ram1_rd_addr)     ,
    .data_out     (data_out)     ,
    .ram2_wr_en   (ram2_wr_en)     ,
    .ram2_wr_addr (ram2_wr_addr)     ,
    .ram2_wr_data (ram2_wr_data)     ,
    .ram2_rd_en   (ram2_rd_en)     ,
    .ram2_rd_addr (ram2_rd_addr)

);

ram	ram_inst1 
(
	.data ( ram1_wr_data ),
	.rdaddress ( ram1_rd_addr ),
	.rdclock ( clk_25m ),
	.rden ( ram1_rd_en ),
	.wraddress ( ram1_wr_addr ),
	.wrclock ( clk_50m ),
	.wren ( ram1_wr_en ),
    
	.q ( ram1_rd_data )
	);

ram	ram_inst2 
(
	.data ( ram2_wr_data ),
	.rdaddress ( ram2_rd_addr ),
	.rdclock ( clk_