module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
reg state,next_state;
parameter IDLE = 1'b0,
DATA = 1'b1;
reg [1:0] count;
reg [1:0] serial;
reg z_reg;
always @(*) begin
next_state = (state==IDLE) ? (s ? DATA : IDLE) : DATA;
end
always @(posedge clk) begin
if(reset) begin
count<=2'b0;
state<=IDLE;
z_reg<=1'b0;
serial<=2'b00;
end
else begin
state<=next_state;
case(state)
IDLE:begin
z_reg<=1'b0;
count<=2'b00;
serial<=0;
end
DATA:begin
if(count==2'b10) begin
count <= 2'b00;
serial <= 2'b00;
if((serial==2'b01) & w)
z_reg<=1;
else if((serial==2'b10) & !w )
z_reg<=1;
else
z_reg <=0;
end
else begin
count<=count+1'b1;
z_reg <= 0 ;
if(w)
serial <= serial+1'b1;
else
serial <= serial;
end
end
endcase
end
end
assign z = z_reg;
endmodule
题目要求尽可能减少状态,故用Melay状态机,两个状态。
IDLE和DATA收发数据状态。