Risc-v E203学习记录

标准DFF模块 

module sirv_gnrl_dfflr # (
  parameter DW = 32                //data width
) (

  input               lden,        //load-enable
  input      [DW-1:0] dnxt,        //D:data in
  output     [DW-1:0] qout,        //Q:data out
    
  input               clk,
  input               rst_n        //reset, active low, 0
);

reg [DW-1:0] qout_r;                

always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
  if (rst_n == 1'b0)
    qout_r <= {DW{1'b0}};
  else if (lden == 1'b1)
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
  .DW(1)
) sirv_gnrl_xchecker(
  .i_dat(lden),
  .clk  (clk)
);
//synopsys translate_on
`endif//}
`endif//}
    

endmodule



//Verilog if-else can't transmit X signal,
//so we should use assertion to catch the X value


`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
module sirv_gnrl_xchecker # (
  parameter DW = 32
) (
  input  [DW-1:0] i_dat,
  input clk
);


CHECK_THE_X_VALUE:
  assert property (@(posedge clk) 
                     ((^(i_dat)) !== 1'bx)
                  )
  else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");

endmodule
//synopsys translate_on
`endif//}
`endif//}

并发断言

labels: assert property (判断条件)

a_b: assert property(@(posedge clk) not(a && b));

labels为断言名称；

property（属性）在每个时钟的上升沿都被效验，不论a和b如何变化。

assert property (@(posedge clk)

                     ((^(i_dat)) !== 1'bx)

                  )

  else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");

时钟沿上升，判断条件(  (^(i_dat)) !== 1'bx  )      ，即判断是否有不定态，若没有，则条件为真，空操作；若有X，则条件为假，输出错误信息 Error