fpga verilog 学习 跑马灯

基于vivado以实现led_run为案例

led_run.v

module led_run(
        Clk,
        Reset_n,
        Led
        );
        
        input Clk;
        input Reset_n;
        output reg[7:0]Led;
        
        reg [24:0]counter;
        
        always@(posedge Clk or negedge Reset_n)
        if(!Reset_n)
            counter <= 0;
        else if(counter == 24999999)
            counter <= 0;
        else
            counter <= counter +  1'b1;
            
        always@(posedge Clk or negedge Reset_n)
        if(!Reset_n)
            Led <= 8'b0000_0001;
        else if(counter == 24999999)begin
            if(Led == 8'b1000_0000)
                Led <= 8'b0000_0001;
            else 
               Led <= Led<<1;
         end
         else
             Led <= Led;
endmodule

        reg [2:0]counter2;    
        always@(posedge Clk or negedge Reset_n)
        if(!Reset_n)
            counter2 <= 0;
        else if(counter == 24999)
            counter2 <= counter2 + 1'b1;
            
       decoder_3_8 decoder_3_8(
                .a(counter2[2]),
                .b(counter2[1]),
                .c(counter2[0]),
                .out(Led));

 

        always@(posedge Clk or negedge Reset_n)
        if(!Reset_n)
            Led <= 8'b0000_0001;
        else if(counter == 24999999)
            Led <= {Led[6:0],Led[7]};
        else
             Led <= Led;

led_run_tb.v

`timescale 1ns/1ns

module led_run_tb;

    reg Clk;
    reg Reset_n;
    wire [7:0]Led;
    
    led_run2 led_run(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Led(Led)
    );
    
    initial Clk = 1;
    always #10 Clk = ~Clk;
    
    initial begin
    Reset_n = 0;
    #201;
    Reset_n = 1;
    #40000000;
    $stop;
    end
endmodule

学习收获

跑马灯的三种写法  ，调用函数

学习时间

1h

今日推歌

无

今日总结

又摆烂两天，学习效率太低，不能再这样了，明天一定好好学习