目录
第152题：Counter with period 1000
第153题：4-bit shift register and downcounter
第154题：FSM: Sequence 1101recognizer
第155题：FSM: Enable shift register
第158题：FSM: One-hot logic equations
第151题：Q2b:Another FSM
module top_module
(
input clk ,
input resetn , // active-low synchronous reset
input x ,
input y ,
output f ,
output g
);
parameter IDLE = 4'd0;
parameter F_H = 4'd1;
parameter CK_X = 4'd2;
parameter X1 = 4'd3;
parameter X10 = 4'd4;
parameter X101 = 4'd5;
parameter Y_0 = 4'd6;
parameter G_H = 4'd7;
parameter G_L = 4'd8;
reg [3:0] state,next_state;
reg [1:0] count;
always@(*)
case(state)
IDLE : next_state = F_H;//只要复位在，它就一直是idle，这里没有复位才会跳
F_H : next_state = CK_X;//到了fh下一个周期必然进入监测x
CK_X : next_state = x?X1:CK_X;
X1 : next_state = x?X1:X10;
X10 : next_state = x?X101:CK_X;
X101 : next_state = y?G_H:Y_0;//上个周期已经101了，这个周期g已经拉高了，已经开始监测y了
Y_0 : next_state = y?G_H:G_L;
G_H : next_state = G_H;
G_L : next_state = G_L;
default: next_state = IDLE;
endcase
always@(posedge clk)
if(resetn==1'b0)
state <= IDLE;
else
state <= next_state;
assign f = state==F_H;
assign g = state==X101 || state==Y_0 || state==G_H;
endmodule
第152题：Counter with period 1000
module top_module
(
input clk ,
input reset ,
output [9:0] q
);
always@(posedge clk)
if(reset)
q <= 10'd0;
else if(q==999)
q <= 10'd0;
else
q <= q+1'b1;
endmodule第153题：4-bit shift register and downcounter
module top_module
(
input clk ,
input shift_ena ,
input count_ena ,
input data ,
output [3:0] q
);
always@(posedge clk)
if(shift_ena)
q <= {q[2:0],data};
else if(count_ena)
q <= q - 1'b1;
endmodule
第154题：FSM: Sequence 1101recognizer
module top_module
(
input clk ,
input reset , // Synchronous reset
input data ,
output start_shifting
);
parameter IDLE = 3'd0;
parameter ONE = 3'd1;
parameter TWO = 3'd2;
parameter THREE = 3'd3;
parameter FOUR = 3'd4;
reg [2:0] state,next_state;
always@(*)
case(state)
IDLE : next_state = data ? ONE : IDLE;
ONE : next_state = data ? TWO : IDLE;
TWO : next_state = data ? TWO : THREE;
THREE : next_state = data ? FOUR: IDLE;
FOUR : next_state = FOUR;
default: next_state = IDLE;
endcase
always@(posedge clk)
if(reset)
state <= IDLE;
else
state <= next_state;
assign start_shifting = state==FOUR;
endmodule第155题：FSM: Enable shift register
module top_module
(
input clk ,
input reset , // Synchronous reset
output shift_ena
);
reg [2:0] cnt;
always@(posedge clk)
if(reset)
cnt <= 3'd1;
else if(cnt==3'd4)
cnt <= cnt;
else if(shift_ena == 1'b1)
cnt <= cnt + 1'b1;
always@(posedge clk)
if(reset)
shift_ena <= 1'b1;
else if(cnt == 3'd4)
shift_ena <= 1'b0;
endmodule第156题：FSM: The complete FSM
module top_module
(
input clk ,
input reset , // Synchronous reset
input data ,
output shift_ena ,
output counting ,
input done_counting ,
output done ,
input ack
);
parameter S = 4'd0;
parameter S1 = 4'd1;
parameter S11 = 4'd2;
parameter S110 = 4'd3;
parameter B0 = 4'd4;
parameter B1 = 4'd5;
parameter B2 = 4'd6;
parameter B3 = 4'd7;
parameter COUNT = 4'd8;
parameter WAIT = 4'd9;
reg [3:0] state,next_state;
always@(*)
case(state)
S : next_state = data ? S1 : S;
S1 : next_state = data ? S11 : S;
S11 : next_state = data ? S11 : S110;
S110 : next_state = data ? B0 : S;
B0 : next_state = B1;
B1 : next_state = B2;
B2 : next_state = B3;
B3 : next_state = COUNT;
COUNT : next_state = done_counting ? WAIT : COUNT;
WAIT : next_state = ack ? S : WAIT;
default: next_state = S;
endcase
always@(posedge clk)
if(reset)
state <= S;
else
state <= next_state;
assign shift_ena = state==B0 || state==B1 || state==B2 || state==B3;
assign counting = state==COUNT;
assign done = state==WAIT;
endmodule第157题：The complete timer
module top_module
(
input clk ,
input reset , // Synchronous reset
input data ,
output [3:0] count ,
output counting,
output done ,
input ack
);
wire shift_ena;
wire done_counting;
reg [3:0] state,next_state;
parameter S = 4'd0;
parameter S1 = 4'd1;
parameter S11 = 4'd2;
parameter S110 = 4'd3;
parameter B0 = 4'd4;
parameter B1 = 4'd5;
parameter B2 = 4'd6;
parameter B3 = 4'd7;
parameter COUNTING= 4'd8;
parameter DONE = 4'd9;
always@(*)
case(state)
S : next_state = data?S1:S;
S1 : next_state = data?S11:S;
S11 : next_state = data?S11:S110;
S110 : next_state = data?B0:S;
B0 : next_state = B1;
B1 : next_state = B2;
B2 : next_state = B3;
B3 : next_state = COUNTING;
COUNTING : next_state = done_counting?DONE:COUNTING;
DONE : next_state = ack?S:DONE;
default : next_state = S;
endcase
always@(posedge clk)
if(reset)
state <= S;
else
state <= next_state;
assign shift_ena = state==B0 || state==B1 || state==B2 || state==B3;
assign done_counting = count==0 && cnt_1k==999;
assign count = delay;
assign counting = state==COUNTING;
assign done = state==DONE;
reg [3:0] delay;
always@(posedge clk)
if(shift_ena)
delay <= {delay[2:0],data};
else if(cnt_1k == 999)
delay <= delay - 1'b1;
reg [9:0] cnt_1k;
always@(posedge clk)
if(~counting)
cnt_1k <= 10'd0;
else
cnt_1k <= cnt_1k< 999 ? cnt_1k + 1'b1 : 0;
endmodule第158题：FSM: One-hot logic equations
module top_module
(
input d ,
input done_counting ,
input ack ,
input [9:0] state , // 10-bit one-hot current state
output B3_next ,
output S_next ,
output S1_next ,
output Count_next ,
output Wait_next ,
output done ,
output counting ,
output shift_ena
);
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = ~d & state[S] | ~d & state[S1] | ~d & state[S110] | ack & state[Wait];
assign S1_next = d & state[S];
assign Count_next = state[B3] | ~done_counting & state[Count];
assign Wait_next = done_counting & state[Count] | ~ack & state[Wait];
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3];
endmodule第159题：MuX
module top_module
(
input sel ,
input [7:0] a ,
input [7:0] b ,
output [7:0] out
);
assign out = sel ? a : b;
endmodule第160题：NAND
module top_module (input a, input b, input c, output out);
wire w_out;
andgate inst1 (w_out, a, b, c, 1'b1, 1'b1 );
assign out = ~w_out;
endmodule
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