第一个工程:
module and_or_not
(
input wire a,
input wire b,
output wire c,
output wire d,
output wire e
)
assign c = a&b;
assign d = a|b;
assign e = ~a;
endmodule
这里assign语句一般是用于组合逻辑赋值,&表示按位与,|按位或,~按位取反,还有assign语句输出变量类型必须是线网型,接下来写一下仿真代码:
`timescale 1ns / 1ps
module tb_and_or_not();
//Reg define
reg sys_clk;
reg sys_rst_n;
reg a;
reg b;
//Wire define
wire c;
wire d;
wire e;
initial
begin
sys_clk = 1'b0;
sys_rst_n = 1'b0;
//变量a,b初始化为0
a = 1'b0;
b = 1'b0;
#200
sys_rst_n = 1'b1;
a = 1'b0;
b = 1'b1;
#200
a = 1'b1;
b = 1'b0;
#200
a = 1'b1;
b = 1'b0;
end
always #10 sys_clk = ~sys_clk;//每10ns时钟翻转一次
and_or_not and_or_not_inst//例化
(
.a (a),
.b (b),
.c (c),
.d (d),
.e (e)
);
endmodule
仿真如下:
看看RTL视图