Xilinx SRIO IP（Serial RapidIO）学习心得（二）: example design 总体介绍说明

ip生成 

默认配置

选择第一个

打开example design

设计总体如下图所示

先介绍一下各个模块的的功能

 srio_example_top.v ：示例设计的顶层HDL文件，连接各个子模块。

 srio_support.v ：时钟，复位和srio IP实例化的HDL包装文件。

 srio_request_gen.v ：此模块生成要发送到链路合作伙伴的请求事务。它用事务类型参数化，因此只发送适合于端口并由核心支持的事务。

srio_response_gen.v ：此文件包含创建对传入事务的响应的逻辑（如果它们是生成响应的数据包类型） 

srio_quick_start.v      ： 在srio_example_top中实例化的srio_quick_start模块可连接到维护端口并生成维护事务。您可以通过编辑maintenance_list文件来添加、修改或删除事务

srio_statistics.v         ： 该文件从核心收集统计数据，并通过寄存器接口传递信息，可通过Vivado设计套件调试特性或用户设计进行访问

srio_report.v            ： 此文件在传输和/或接收数据包时显示。

总体数据流如下图所示

通过以上设置该ip一共生成了4组AXI_Stream接口，和一组AXI_Lite接口 打开例化文件

如下所示 axi接口 依次是

s_axis_ireq    : 表示Initiator请求事务的传输通道（i = initiator ,req = request）  

m_axis_iresp : 表示Initiator响应事务的传输通道（i = initiator ,resp = response）    

m_axis_ireq  : 表示Target请求事务的传输通道（t = target ,req = request）   

s_axis_iresp : 表示Target响应事务的传输通道（t = target , resp = response）

s_axi_maintr: 维护接口，采用AXI4-Lite接口，示维护事务的传输端口（maintr = maintenance）

srio_gen2_0 your_instance_name (
        .log_clk_in                     ( log_clk_in                            ), // input wire log_clk_in
        .buf_rst_in                     ( buf_rst_in                            ), // input wire buf_rst_in
        .log_rst_in                     ( log_rst_in                            ), // input wire log_rst_in
        .gt_pcs_rst_in                  ( gt_pcs_rst_in                         ), // input wire gt_pcs_rst_in
        .gt_pcs_clk_in                  ( gt_pcs_clk_in                         ), // input wire gt_pcs_clk_in
        .cfg_rst_in                     ( cfg_rst_in                            ), // input wire cfg_rst_in
        .deviceid                       ( deviceid                              ), // output wire [15 : 0] deviceid
        .port_decode_error              ( port_decode_error                     ), // output wire port_decode_error

        .s_axis_ireq_tvalid             ( s_axis_ireq_tvalid                    ), // input wire s_axis_ireq_tvalid
        .s_axis_ireq_tready             ( s_axis_ireq_tready                    ), // output wire s_axis_ireq_tready
        .s_axis_ireq_tlast              ( s_axis_ireq_tlast                     ), // input wire s_axis_ireq_tlast
        .s_axis_ireq_tdata              ( s_axis_ireq_tdata                     ), // input wire [63 : 0] s_axis_ireq_tdata
        .s_axis_ireq_tkeep              ( s_axis_ireq_tkeep                     ), // input wire [7 : 0] s_axis_ireq_tkeep
        .s_axis_ireq_tuser              ( s_axis_ireq_tuser                     ), // input wire [31 : 0] s_axis_ireq_tuser

        .m_axis_iresp_tvalid            ( m_axis_iresp_tvalid                   ), // output wire m_axis_iresp_tvalid
        .m_axis_iresp_tready            ( m_axis_iresp_tready                   ), // input wire m_axis_iresp_tready
        .m_axis_iresp_tlast             ( m_axis_iresp_tlast                    ), // output wire m_axis_iresp_tlast
        .m_axis_iresp_tdata             ( m_axis_iresp_tdata                    ), // output wire [63 : 0] m_axis_iresp_tdata
        .m_axis_iresp_tkeep             ( m_axis_iresp_tkeep                    ), // output wire [7 : 0] m_axis_iresp_tkeep
        .m_axis_iresp_tuser             ( m_axis_iresp_tuser                    ), // output wire [31 : 0] m_axis_iresp_tuser

        .m_axis_treq_tvalid             ( m_axis_treq_tvalid                    ), // output wire m_axis_treq_tvalid
        .m_axis_treq_tready             ( m_axis_treq_tready                    ), // input wire m_axis_treq_tready
        .m_axis_treq_tlast              ( m_axis_treq_tlast                     ), // output wire m_axis_treq_tlast
        .m_axis_treq_tdata              ( m_axis_treq_tdata                     ), // output wire [63 : 0] m_axis_treq_tdata
        .m_axis_treq_tkeep              ( m_axis_treq_tkeep                     ), // output wire [7 : 0] m_axis_treq_tkeep
        .m_axis_treq_tuser              ( m_axis_treq_tuser                     ), // output wire [31 : 0] m_axis_treq_tuser

        .s_axis_tresp_tvalid            ( s_axis_tresp_tvalid                   ), // input wire s_axis_tresp_tvalid
        .s_axis_tresp_tready            ( s_axis_tresp_tready                   ), // output wire s_axis_tresp_tready
        .s_axis_tresp_tlast             ( s_axis_tresp_tlast                    ), // input wire s_axis_tresp_tlast
        .s_axis_tresp_tdata             ( s_axis_tresp_tdata                    ), // input wire [63 : 0] s_axis_tresp_tdata
        .s_axis_tresp_tkeep             ( s_axis_tresp_tkeep                    ), // input wire [7 : 0] s_axis_tresp_tkeep
        .s_axis_tresp_tuser             ( s_axis_tresp_tuser                    ), // input wire [31 : 0] s_axis_tresp_tuser

        .s_axi_maintr_rst               ( s_axi_maintr_rst                      ), // input wire s_axi_maintr_rst
        .s_axi_maintr_awvalid           ( s_axi_maintr_awvalid                  ), // input wire s_axi_maintr_awvalid
        .s_axi_maintr_awready           ( s_axi_maintr_awready                  ), // output wire s_axi_maintr_awready
        .s_axi_maintr_awaddr            ( s_axi_maintr_awaddr                   ), // input wire [31 : 0] s_axi_maintr_awaddr
        .s_axi_maintr_wvalid            ( s_axi_maintr_wvalid                   ), // input wire s_axi_maintr_wvalid
        .s_axi_maintr_wready            ( s_axi_maintr_wready                   ), // output wire s_axi_maintr_wready
        .s_axi_maintr_wdata             ( s_axi_maintr_wdata                    ), // input wire [31 : 0] s_axi_maintr_wdata
        .s_axi_maintr_bvalid            ( s_axi_maintr_bvalid                   ), // output wire s_axi_maintr_bvalid
        .s_axi_maintr_bready            ( s_axi_maintr_bready                   ), // input wire s_axi_maintr_bready
        .s_axi_maintr_bresp             ( s_axi_maintr_bresp                    ), // output wire [1 : 0] s_axi_maintr_bresp
        .s_axi_maintr_arvalid           ( s_axi_maintr_arvalid                  ), // input wire s_axi_maintr_arvalid
        .s_axi_maintr_arready           ( s_axi_maintr_arready                  ), // output wire s_axi_maintr_arready
        .s_axi_maintr_araddr            ( s_axi_maintr_araddr                   ), // input wire [31 : 0] s_axi_maintr_araddr
        .s_axi_maintr_rvalid            ( s_axi_maintr_rvalid                   ), // output wire s_axi_maintr_rvalid
        .s_axi_maintr_rready            ( s_axi_maintr_rready                   ), // input wire s_axi_maintr_rready
        .s_axi_maintr_rdata             ( s_axi_maintr_rdata                    ), // output wire [31 : 0] s_axi_maintr_rdata
        .s_axi_maintr_rresp             ( s_axi_maintr_rresp                    ), // output wire [1 : 0] s_axi_maintr_rresp

        .gt_clk_in                      ( gt_clk_in                             ), // input wire gt_clk_in
        .refclk_in                      ( refclk_in                             ), // input wire refclk_in
        .buf_lcl_response_only_out      ( buf_lcl_response_only_out             ), // output wire buf_lcl_response_only_out
        .buf_lcl_tx_flow_control_out    ( buf_lcl_tx_flow_control_out           ), // output wire buf_lcl_tx_flow_control_out
        .idle2_selected                 ( idle2_selected                        ), // output wire idle2_selected
        .idle_selected                  ( idle_selected                         ), // output wire idle_selected
        .buf_lcl_phy_buf_stat_out       ( buf_lcl_phy_buf_stat_out              ), // output wire [5 : 0] buf_lcl_phy_buf_stat_out
        .phy_clk_in                     ( phy_clk_in                            ), // input wire phy_clk_in
        .gtrx_reset_done_out            ( gtrx_reset_done_out                   ), // output wire gtrx_reset_done_out
        .gtpowergood_out                ( gtpowergood_out                       ), // output wire [0 : 0] gtpowergood_out
        .txoutclk                       ( txoutclk                              ), // output wire txoutclk
        .freerun_clk                    ( freerun_clk                           ), // input wire freerun_clk
        .gt_rst                         ( gt_rst                                ), // input wire gt_rst
        .phy_rst_in                     ( phy_rst_in                            ), // input wire phy_rst_in
        .sim_train_en                   ( sim_train_en                          ), // input wire sim_train_en
        .phy_mce                        ( phy_mce                               ), // input wire phy_mce
        .phy_link_reset                 ( phy_link_reset                        ), // input wire phy_link_reset
        .force_reinit                   ( force_reinit                          ), // input wire force_reinit
        .phy_lcl_phy_next_fm_out        ( phy_lcl_phy_next_fm_out               ), // output wire [5 : 0] phy_lcl_phy_next_fm_out
        .phy_lcl_phy_last_ack_out       ( phy_lcl_phy_last_ack_out              ), // output wire [5 : 0] phy_lcl_phy_last_ack_out
        .link_initialized               ( link_initialized                      ), // output wire link_initialized
        .phy_lcl_phy_rewind_out         ( phy_lcl_phy_rewind_out                ), // output wire phy_lcl_phy_rewind_out
        .phy_lcl_phy_rcvd_buf_stat_out  ( phy_lcl_phy_rcvd_buf_stat_out         ), // output wire [5 : 0] phy_lcl_phy_rcvd_buf_stat_out
        .phy_rcvd_mce                   ( phy_rcvd_mce                          ), // output wire phy_rcvd_mce
        .phy_rcvd_link_reset            ( phy_rcvd_link_reset                   ), // output wire phy_rcvd_link_reset
        .port_error                     ( port_error                            ), // output wire port_error
        .port_initialized               ( port_initialized                      ), // output wire port_initialized
        .clk_lock_in                    ( clk_lock_in                           ), // input wire clk_lock_in
        .mode_1x                        ( mode_1x                               ), // output wire mode_1x
        .port_timeout                   ( port_timeout                          ), // output wire [23 : 0] port_timeout
        .srio_host                      ( srio_host                             ), // output wire srio_host
        .phy_lcl_master_enable_out      ( phy_lcl_master_enable_out             ), // output wire phy_lcl_master_enable_out
        .phy_lcl_maint_only_out         ( phy_lcl_maint_only_out                ), // output wire phy_lcl_maint_only_out
        .gtrx_disperr_or                ( gtrx_disperr_or                       ), // output wire gtrx_disperr_or
        .gtrx_notintable_or             ( gtrx_notintable_or                    ), // output wire gtrx_notintable_or
        .phy_debug                      ( phy_debug                             ), // output wire [223 : 0] phy_debug
        .srio_txn0                      ( srio_txn0                             ), // output wire srio_txn0
        .srio_txp0                      ( srio_txp0                             ), // output wire srio_txp0
        .srio_rxn0                      ( srio_rxn0                             ), // input wire srio_rxn0
        .srio_rxp0                      ( srio_rxp0                             )  // input wire srio_rxp0
);

下一章介绍具体模块的功能和代码