XILINX脉冲同步代码（取自某IP example design）

//Pulse sychronizer Logic
generate if (c_cdc_type == 0) begin
    always @ (posedge prmry_aclk)
    begin: REG_P_IN
    	if ( (prmry_rst_n == 1'b0) & (c_reset_state == 1) )
    	begin
    	    p_in_dl_cdc_from <= 1'b0;
    	end
    	else
    	begin
            p_in_dl_cdc_from <= prmry_in ^ p_in_dl_cdc_from;
        end
    end

    always @ ( posedge scdry_aclk)
    begin:P_IN_CROSS2SNDRY
    	if ( (scndry_rst_n == 1'b0) & (c_reset_state == 1) ）
    	begin
    	    s_out_dl_cdc_to <= 1'b0;
    	    s_out_d2 <= 1'b0;
    	    s_out_d3 <= 1'b0;
    	    s_out_d4 <= 1'b0;
    	    s_out_d5 <= 1'b0;
    	    s_out_d6 <= 1'b0;
    	    s_out_d7 <= 1'b0;
    	    scndry_out_int_dl <= 1'b0;
    	end
    	else
    	begin
    	    s_out_dl_cdc_to <= p_in_dl_cdc_from;
    	    s_out_d2 <= s_out_dl_cdc_to;
    	    s_out_d3 <= s_out_d2;
    	    s_out_d4 <= s_out_d3;
    	    s_out_d5 <= s_out_d4;
    	    s_out_d6 <= s_out_d5;
    	    s_out_d7 <= s_out_d6;
    	    scndry_out_int_dl <= s_out_re;
    	end
    end
    assign scndry_out = scndry_out_int_dl;
    assign prmry_ack = 1'b0;
    assign scndry_vect_out = 0;
end
endgenerate

generate if (c_mtbf_stage == 2 & c_cdc_type == 0) begin
	assign s_out_re = ( s_out_d2 ^ s_out_d3 );
end
endgenerate

generate if (c_mtbf_stage == 3 & c_cdc_type == 0) begin
	assign s_out_re = ( s_out_d3 ^ s_out_d4 );
end
endgenerate

generate if (c_mtbf_stage == 4 & c_cdc_type == 0) begin
	assign s_out_re = ( s_out_d4 ^ s_out_d5 );
end
endgenerate

generate if (c_mtbf_stage == 5 & c_cdc_type == 0) begin
	assign s_out_re = ( s_out_d5 ^ s_out_d6 );
end
endgenerate

generate if (c_mtbf_stage == 6 & c_cdc_type == 0) begin
	assign s_out_re = ( s_out_d6 ^ s_out_d7 );
end
endgenerate