XILINX脉冲同步代码
//Pulse sychronizer Logic
generate if (c_cdc_type == 0) begin
always @ (posedge prmry_aclk)
begin: REG_P_IN
if ( (prmry_rst_n == 1'b0) & (c_reset_state == 1) )
begin
p_in_dl_cdc_from <= 1'b0;
end
else
begin
p_in_dl_cdc_from <= prmry_in ^ p_in_dl_cdc_from;
end
end
always @ ( posedge scdry_aclk)