50MHz分频为1Hz

module div(clk_in,rst_n,clk_out);
    input clk_in;
    input rst_n;
    output clk_out;
    reg clk_out;

    reg [25:0] cnt;
    
    always @(posedge clk_in or negedge rst_n)
    begin
    if(!rst_n)
        cnt <= 0;
    else if(cnt == 50_000_000-1)
        cnt <= 0;
    else 
        cnt<= cnt+1;
    end

    always @(posedge clk_in or negedge rst_n)
    begin
    if(!rst_n)
        clk_out <= 0;
    else if((cnt == 25_000_000-1)||(cnt == 50_000_000-1))
        clk_out <= ~clk_out;
    else 
        clk_out <= clk_out;
    end

endmodule