verilog将100mhz分频为1hz_分频程序(50Mhz-1Hz)

数字电路课程设计功能款程序

library ieee; use ieee.std_logic_1164.all; entity fen is port (clk:in std_logic; q: out std_logic); end fen; architecture fen_arc of fen is begin process(clk) variable cnt: integer range 0 to 24999999; variable x: std_logic; begin if clk'event and clk = '1' then if cnt<24999999 then cnt:=cnt+1; else cnt:=0; x:= not x; end if; end if; q<=x; end process; end fen_arc;

该程序是将50MHz的频率变成1Hz的频率，若要分成其他频率的信号，自己修改程序。