开发环境:Quartus Prime 18.0
设备:小脚丫开发板,搭载AlteraMAX10 10M02SCM153C8G
语言:verilog HDL
程序效果:实现两位数码管以十进制显示数字,并且可以2-100进制进行加法计数,带清零rst和保持hold的功能
主代码
module inc_counter#(
parameter CNT_SIZE=8,
parameter BASE_HIGH=4,
parameter BASE_LOW=6//进制2-100,进制100时此值取10
)
(
input clk,rst,hold,
output wire [17:0] seg
);
reg [CNT_SIZE/2-1:0]cnt_high;
reg [CNT_SIZE/2-1:0]cnt_low;
reg VDD;
initial VDD=1;
divider #(.N(6000000),.WIDTH(24))divider1(
.clk(clk),
.rst(VDD),
.clk_out(clk1)
);
segment7 high(.A(cnt_high[CNT_SIZE/2-1:0]),.g_to_a(seg[17:9]));
segment7 low(.A(cnt_low[CNT_SIZE/2-1:0]),.g_to_a(seg[8:0]));
always @(posedge clk1, negedge rst, negedge hold)
if(!rst)
begin
cnt_high<=0;
cnt_low<=0;
end
else if(!hold)
begin
cnt_high<=cnt_high;
cnt_low<=cnt_low;
end
else
if(cnt_high == BASE_HIGH)
if(cnt_low == BASE_LOW-1)
begin
cnt_high<=0;
cnt_low<=0;
end
else cnt_low<=cnt_low+1'b1;
else
if(cnt_low == 10-1)
begin
cnt_high<=cnt_high+1'b1;
cnt_low<=0;
end
else cnt_low<=cnt_low+1'b1;
endmodule
分配管脚:
调用的子模块:
1.数码管segment7
module segment7(
input wire [3:0] A,
output wire [8:0] g_to_a
);
reg [8:0] seg[15:0];
initial
begin
seg[4'b0000]=9'h3f;
seg[4'b0001]=9'h06;
seg[4'b0010]=9'h5b;
seg[4'b0011]=9'h4f;
seg[4'b0100]=9'h66;
seg[4'b0101]=9'h6d;
seg[4'b0110]=9'h7d;
seg[4'b0111]=9'h07;
seg[4'b1000]=9'h7f;
seg[4'b1001]=9'h6f;
seg[4'b1010]=9'h77;
seg[4'b1011]=9'h7c;
seg[4'b1100]=9'h39;
seg[4'b1101]=9'h5e;
seg[4'b1110]=9'h79;
seg[4'b1111]=9'h71;
end
assign g_to_a = seg[A];
endmodule
2.分频器divider
module divider(
inout clk,
input rst,
output reg clk_out
);
parameter N=6000000,WIDTH=24;
reg [WIDTH-1:0] cnt;
always @(posedge(clk),posedge(rst))
begin
if(rst==1'b1)
cnt<=24'b0;
else if(cnt==N-1)
cnt<=24'b0;
else
cnt<=cnt+1;
end
always @(posedge(clk),posedge(rst))
begin
if(rst==1'b1)
clk_out<=1'b0;
else if(cnt==N-1)
clk_out<=~clk_out;
else
clk_out<=clk_out;
end
endmodule