RT-Thread源码详解(二)------红外遥控

最新推荐文章于 2024-08-22 16:30:02 发布

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最新推荐文章于 2024-08-22 16:30:02 发布

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分类专栏： RT-Thread 文章标签：嵌入式 RTOS RT-Thread 物联网

本文链接：https://blog.csdn.net/renqingxin2011/article/details/94555207

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本文详细介绍了如何利用RT-Thread在STM32上实现红外遥控的接收与发送，并深入探讨了RT-Thread的ulog日志组件，包括其功能、软件架构、日志级别和标签系统，强调了ulog的资源占用低、线程安全和高可靠性等特点。

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本文介绍通过控制潘多拉开发板实现红外遥控的接收与发送。要实现红外遥控的接收与发送只需要使用stm32内部定时器控制外部管脚变化产生38kHz的方波，以此控制相应的红外接收与发射接口，就可以实现红外控制。
代码讲解：

//#define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
//#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
//#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
//#define RCC                 ((RCC_TypeDef *) RCC_BASE)
/*
typedef struct
{
  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
  __IO uint32_t APB1ENR1