一种三分频电路的实现与仿真

module fenpin;
  reg clk;
  reg q1;
  reg q2;
  wire d1,d2;
  
  initial begin
    clk = 0;
    q1 = 0;
    q2 = 0;
  end
  
  always #10 clk = ~ clk;
  
  always @(posedge clk)
    q1<=d1;
    
  always @(posedge clk)
    q2<=d2;
  
  assign d2 = ~q1;
  assign d1 = q2 & ~q1;
  
endmodule