Verilog刷题笔记53

题目：
Fsm serialdata
See also: Serial receiver

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don’t-care otherwise.

解题:

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter idle=0,start=1,data_receive=2,stop=3,error=4;
    reg [2:0]state,next_state;
    reg [3:0]cnt;
    reg [7:0]out;
    always@(posedge clk)begin
        if(reset)
            state=idle;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            idle:next_state=(in==0)?start:idle;
            start:next_state=data_receive;
            data_receive:next_state=(cnt==8)?(in?stop:error):data_receive;
            stop:next_state=in?idle:start;
            error:next_state=in?idle:error;
            default:next_state=idle;
        endcase
    end
    always@(posedge clk)begin
        if(reset)
            cnt=0;
        else begin
            case(next_state)
                start:cnt=0;
                data_receive:cnt=cnt+1;
                default:cnt=cnt;
            endcase
        end
    end
    always@(posedge clk)begin
        if(reset)
            out=0;
        else begin
            case(next_state)
                start:out=0;
                data_receive:out={in,out[7:1]};
            endcase
        end
    end
    assign done=(state==stop)?1:0;
    assign out_byte=out;

    // Use FSM from Fsm_serial

    // New: Datapath to latch input bits.

endmodule

结果正确：

本题在51、52题目的基础上增加了记录数据、计周期数的功能。
即51、52两道题目的结合体。