Verilog刷题笔记55

题目：
Exams/ece241 2014 q5a
You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2’s complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.

解题：

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter s0=0,s1=1,s2=2,s3=3;
    reg [1:0]state,next_state;
    always@(posedge clk or posedge areset)begin
        if(areset)
            state=s0;
        else 
            state=next_state;
    end
    always@(*)begin
        case(state)
            s0:next_state=x?s1:s0;
            s1:next_state=x?s2:s3;
            s2:next_state=x?s2:s3;
            s3:next_state=x?s2:s3;
        endcase
    end
    always@(*)begin
        case(state)
            s0:z=0;
            s1:z=1;
            s2:z=0;
            s3:z=1;
        endcase
    end
        
            
   
endmodule

结果正确:

知识点:
负数补码规则，负数原码最高位（符号位）不变，其余位取反得到反码，反码加 1 得到补码。
通过观察，本题原码转换为补码有这样一个简单规律：从最低位开始一直到遇到的第一个 1 （例如 100）保持不变（仍为 100），之后一律按位取反。