Verilog刷题笔记60

题目：
Exams/2013 q2bfsm
Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

解题：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8;
    reg [3:0]state,next_state;
    always@(posedge clk)begin
        if(!resetn)
            state=s0;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            s0:next_state=s8;
            s8:next_state=s1;
            s1:next_state=x?s2:s1;
            s2:next_state=x?s2:s3;
            s3:next_state=x?s4:s1;
            s4:next_state=y?s6:s5;
            s5:next_state=y?s6:s7;
            s6:next_state=s6;
            s7:next_state=s7;
        endcase
    end

    assign f=(state==s8);
    assign g=(state==s4)|(state==s5)|(state==s6);


endmodule

结果正确：

注意点：
专门用一个状态，来表示f置为1 只有一个时钟周期。