PIPE学习记录

PIPE Introduction

PIPE (PHY Interface for PCI Express): Actually, PIPE is a standard interface which is not only design for PCIe but also for USB/SATA/DP/Converge IO. It is the interface between MAC and PHY.

• PCLK is the clocking for each lane. There are two PCLK mode.
  – PCLK as output for PHY: This mode is no longer user for PCIe Gen5 and beyond.
  – PCLK as input for PHY: This mode is introduced from 4.1 version. PCLK as input allows controller and external logic more easily adjust timing in the silicon.
  Refer PIPE Spec 6.1 for signals description

PIPE Mode

Before introduce PIPE mode, it is nessary to introduce function block of PHY.
Note: Below screenshot is per lane function. So PCLK should be separate for each lane.

Compared to Original PIPE mode, Serdes PIPE mode move 8b/10b (128b/130b) encode/decode in PHY to MAC. Diagrams are shown in next sections.

Original PIPE Mode

Transmitter block in Gen1/Gen2

Transmitter block in Gen3/Gen4/Gen5

Receiver Block in Gen1/Gen2

Reciever Block in Gen3/Gen4/Gen5

Serdes PIPE Mode

Because encoding logic is move to MAK, there is no differences among all Generations.

Transmitter Block

Receiver Block

Message Bus

Message Bus and Its Superiority Compared to Wires

   Message Bus is design for no-latency sensitive PIPE options (usually refer to register write/read). Message Bus use commands encode to do PIPE options which decreases wires. And it allows to add additional options without increase wires. From the introduction above, we can see the superiority compared to use wires do PIPE options. Because message bus use commands to do PIPE options, it increase the latency which can be explained in next section Message Bus Commands and Message Bus Timing.

Message Bus Interface

   Message Bus provides two group 8bits wires to comminicate between MAC and PHY. The PHY and MAC registers use 12bits addr, so 8bits Message Bus should be map to 12bits addr which will be introduced in Message Bus Commands.

Name	Direction	Description
M2P_MessageBus[7:0]	Input	The Mac multiplex Commands, any required addr, and any required data for sending read and write requests to access PHY registers and for sending read completion and write ack to PHY initiated requests.
P2M_MessageBus[7:0]	Output	The PHY multiplex Commands, any required addr, and any required data for sending read and write requests to access Mac registers and for sending read completion and write ack to Mac initiated requests.

Note that direction above table is refer to PHY

Message Bus Commands

   Message Bus Commands can be divided into three types by the num of cycles one command finish.

• One Cycle: commands no address and no data required
     These commands include write_ack/NOP
  

• Two Cycles: Commands no address required or no data required
     These commands include read_request/read_completion
  
  

• Three Cycles: Commands address and data required.
     These commands include write_commited/write_uncommited.
     From above, we can see that cmd are 4bits encode. The description for cmds are shown below:

Endcoding	Command	Cycles to Transmit
4’b0000	NOP	1
4’b0001	write_uncommited	3
4’b0010	write_commited	3
4’b0011	read	2
4’b0100	read_completion	2
4’b0101	write_ack	1
else	reserved	NA

   Commands above are driven by pclk and easy understand except write_uncommited and write_commited command.

• write_uncommited: There are some registers which need to be updated at the same clk. So write_uncommited command is designed for these type registers. Registers value are stored in buffer by write_uncommited commands and are not effective until write_commited command comes. When write_commited command come, all write_uncommited commands and the lastest write_commit command take effect right now. This mechine ensure these registers take effect at the same clk.
• write_commited: When write_commited command comes, all write_uncommited commands and the lastest write_commited command take effect right now.

Message Bus Timing

1. All zero are driven when bus is idle
2. The data are associated within one transaction must be transfered in contiguous cycles.