深度为8，位宽为8bit的单端口RAM

单端口RAM只有一套地址总线，读操作和写操作是分开的。

module ram_single(clk,addm,cs_n,we_n,din,dout);
	input clk,cs_n,we_n;
	input [2:0] addm;
	input [7:0] din;
	output [7:0] dout;
	reg [7:0] dout;
	reg [7:0] raml [7:0];  //8*8寄存器


	always @ (posedge clk) begin 
		if(cs_n)
			dout <= 8'bzzzz_zzzz;
		else if(we_n)
			dout <= raml[addm];
		else
			raml[addm] <= din;
	end
	
endmodule


`timescale 1ns/1ns

module ram_single_tb;
	reg clk,we_n,cs_n;
	reg [2:0] addm;
	reg [7:0] din;
	wire [7:0] dout;

	ram_single n1 (clk,addm,cs_n,we_n,din,dout);
	
	initial begin
		clk = 0;
		addm = 0;
		cs_n = 1;
		we_n = 0;
		din = 0;
	#5	cs_n = 0;
	#915	we_n = 1;
	end
	always begin
		#10 clk = ~clk;
	end
	initial begin
		repeat(7) begin
			#40 addm = addm+1;
			    din = din +1;
		end
			#40 repeat (7)
				#40 addm = addm-1;
	end

		//#200 $finish;
endmodule