QuartusII18.0/Simulation Wavform Editor与Modelsim10.1d协同的设置

“d:/altera/18.0/quartus/eda/xxx.v” should change to yourselves direction.
下面对应cyclone10lp,其他系列请修改库文件“cyclone10lp_ver”

QuartusII18.0/Simulation Wavform Editor/Simulation Setting/Functional Simulation/Modelsim Script

onerror {exit -code 1}
vlib work
if ![file isdirectory verilog_libs] {
	file mkdir verilog_libs
}

vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {d:/altera/18.0/quartus/eda/sim_lib/altera_primitives.v}

vlib verilog_libs/lpm_ver
vmap lpm_ver ./verilog_libs/lpm_ver
vlog -vlog01compat -work lpm_ver {d:/altera/18.0/quartus/eda/sim_lib/220model.v}

vlib verilog_libs/sgate_ver
vmap sgate_ver ./verilog_libs/sgate_ver
vlog -vlog01compat -work sgate_ver {d:/altera/18.0/quartus/eda/sim_lib/sgate.v}

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {d:/altera/18.0/quartus/eda/sim_lib/altera_mf.v}

vlib verilog_libs/altera_lnsim_ver
vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
vlog -sv -work altera_lnsim_ver {d:/altera/18.0/quartus/eda/sim_lib/altera_lnsim.sv}

vlib verilog_libs/cyclone10lp_ver
vmap cyclone10lp_ver ./verilog_libs/cyclone10lp_ver
vlog -vlog01compat -work cyclone10lp_ver {d:/altera/18.0/quartus/eda/sim_lib/cyclone10lp_atoms.v}

if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -work work xxx.vo
vlog -work work xxx.vwf.vt
vsim -novopt -c -t 1ps -L cyclone10lp_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.xxx_vlg_vec_tst
vcd file -direction xxx.msim.vcd
vcd add -internal xxx_vlg_vec_tst/*
vcd add -internal xxx_vlg_vec_tst/i1/*
proc simTimestamp {} {
    echo "Simulation time: $::now ps"
    if { [string equal running [runStatus]] } {
        after 2500 simTimestamp
    }
}
after 2500 simTimestamp
run -all
quit -f

QuartusII18.0/Simulation Wavform Editor/Simulation Setting/Timing Simulation/Modelsim Script

onerror {exit -code 1}
vlib work
if ![file isdirectory verilog_libs] {
	file mkdir verilog_libs
}
vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {d:/altera/18.0/quartus/eda/sim_lib/altera_primitives.v}

vlib verilog_libs/cyclone10lp_ver
vmap cyclone10lp_ver ./verilog_libs/cyclone10lp_ver
vlog -vlog01compat -work cyclone10lp_ver {d:/altera/18.0/quartus/eda/sim_lib/cyclone10lp_atoms.v}

if {[file exists gate_work]} {
	vdel -lib gate_work -all
}
vlib gate_work
vmap work gate_work

vlog -work work xxx.vo
vlog -work work xxx.vwf.vt
vsim -novopt -c -t 1ps -L cyclone10lp_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.xxx_vlg_vec_tst
vcd file -direction xxx.msim.vcd
vcd add -internal xxx_vlg_vec_tst/*
vcd add -internal xxx_vlg_vec_tst/i1/*
proc simTimestamp {} {
    echo "Simulation time: $::now ps"
    if { [string equal running [runStatus]] } {
        after 2500 simTimestamp
    }
}
after 2500 simTimestamp
run -all
quit -f