从DDR4芯片名称开始了解DDR4 --- 个人笔记

DDR是一种双倍速率的存储技术,它在时钟的上升沿和下降沿传输数据。内存寻址基于存储阵列,通过行和列地址找到特定单元格。性能指标如CAS延迟(CASLatency)、列地址延迟时间(CL)、行地址到列地址延迟(tRCD)和行地址选通脉冲预充电时间(tRP)对内存性能有直接影响。DDR4-2400的时钟周期为0.83ns,速度率为2400MT/s。

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1、名称型号说明
2、DDR基本原理
3、性能指标说明

1、名称型号说明

名称型号说明以 MT40A1G8WE-083EAAT:B 为例

在这里插入图片描述

2、DDR基本原理

 常说的 DDR,其实是 Double Data Rate 双倍速率,是指在时钟上升沿和下降沿各采一次数据(即一个时钟周期采两次),是一种技术。因为此技术广泛使用在DRAM上,所以习惯将DDR代指存储器。
 DDR内部是一个存储阵列,将其想象成一张表格,先指定一个行,再指定一个列,就可以找到所需的单元格,这就是内存芯片寻址的基本原理。这个单元格可以称为存储单元,那么这个表格(存储阵列)就是 Logic Bank(简称Bank)。
 如果寻址B1\R2\C3,既能找到下图中标注的单元格。
在这里插入图片描述

3、性能指标说明

CAL:Command/Address latency
ODT:Nominal, park, and dynamic on-die termination
DBI:Data bus inversion
CAS: Column Address Strobe Latency,表示读取命令发出后到从列地址读出数据到IO接口的间隔时间。
CL: CAS Latency,列地址延迟时间 ,一般用时钟周期数来表示。CL的延迟对于内存读写性能影响最大,被JEDEC当做内存第一时序中的首位。(PCEVA评测室 https://www.bilibili.com/read/cv11825095 出处:bilibili)。
tRCD: RAS-to-CASDelay,内存行地址传输到列地址的延迟时间。
tRP: Row-prechargeDelay,内存行地址选通脉冲预充电时间。

1、speed rate

高速可以向低速兼容。

在这里插入图片描述

(1)MT/s:MegaTransfers/s,即百万次/秒。

(2)DDR4-2400 CL17 的时钟周期时间为0.83ns,则CL = 17*0.83=14.17ns。

(3)以-083E为例,2400MT/s 即 1*109 / (2400 * 1000000) * 2 = 0.833ns。

持续更新ing

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on datasheet). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
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