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ISE
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ISE遇到的各类问题等
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ISE快捷键&&小技巧
目录快捷键快捷键替换:Ctrl + H撤销:Ctrl + Z前进:Ctrl + Y自动补全:Ctrl + Enter(自动补全关键字和已经定义过的变量名)复制光标所在行:Ctrl + D删除光标所在行:Ctrl + X (只剪贴不粘贴 )注释光标所在行:Alt + C取消注释光标所在行:Shift + Alt + C上移光标所在行:Ctrl + T...原创 2018-09-14 11:43:36 · 7503 阅读 · 0 评论 -
matlab生成fir系数coe,ISE生成fir的IP核,并调用coe文件,ISE仿真后,将结果用matlab仿真
%第一步: fdatool生成滤波器系数,将其量化,并用plot查看幅频响应。N=16; %量化位数,即2的指数Fs=184320000;%量化滤波器系数Q_hb1=round(hb1/max(abs(hb1))*(2^(N-1)-1));hn=Q_hb1;%求滤波器的幅频响应m_hb1=20*log(abs(fft(hb1,1024)))/log(10);m_hb1=m_hb1-m...原创 2018-09-05 15:34:26 · 5227 阅读 · 1 评论 -
ISE修改程序后,不必关闭modelsim重新打开!!!
1、 修改程序后重新仿真。使用命令 do testbench_name.fdo 即可重新加载,不必关掉modelsim重新打开。testbench_name为测试文件的名字。2、 保存当前查看的信号在当前查看的wave界面点击保存,或者file---save format。保存名称自定。重新加载modelsim时,使用命令do wave_name.do 即可重新加载。...原创 2018-07-12 16:15:18 · 5030 阅读 · 5 评论 -
将modelsim波形打印成TXT文件,ISE工程,verilog语言
笔记已修改打印程序如下:reg [15:0] i; always @ (posedge clk_30M72) begin if (rst) i <=0; else if (i<10000) i <= i+1; else i<= 10000;end...原创 2018-05-30 17:03:47 · 1870 阅读 · 5 评论 -
ISE/Vivado 常见问题
Port connections cannot be mixed ordered and named:模块后面多加了逗号。原创 2020-01-17 11:09:40 · 900 阅读 · 0 评论 -
ISE布线出现问题 WARNING:ParHelpers:360 - Design is not completely routed.
WARNING:ParHelpers:360 - Design is not completely routed. GTX_RX0_N_IBUF GTX_RX0_P_IBUF GTX_RX1_N_IBUF GTX_RX1_P_IBUF这个问题没有错误提示,只有warning,但是布线失败。此工程的原因是,将上述四个差分信号加到了cdc中,差分信号是不可以被监...原创 2019-02-21 11:07:35 · 2835 阅读 · 4 评论 -
ISE MAP出错:Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB33 compon
Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB33 component because the site type selected is not compatible.Further explanation:The component type is determined by...原创 2019-01-21 18:36:55 · 9947 阅读 · 9 评论 -
ISE生成bit文件出错:Bitgen:342
Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility...原创 2019-03-26 11:07:12 · 4326 阅读 · 0 评论