鉴于每次modelsim时间长了不用就忘记怎么使用,所以这里就直接写一篇,以后忘记了直接来看这个使用教程
所要仿真的工程只是一个简单的频率输出工程,将输入的50M时钟计数100次翻转一次,然后输出这个时钟
原工程程序
module clk_out_test(
i_clk,
i_rst_n,
clk_out
);
input i_clk;
input i_rst_n;
output clk_out;
reg [6:0] count;
reg clk_out_reg;
always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
count <= 7'd0;
else if(count == 7'd99)
count <= 7'd0;
else
count <= count + 1'b1;
end
always@(posedge i_clk or negedge i_rst_n)begin
if(i_rst_n == 1'b0)
clk_out_reg <= 1'd0;
else if(count == 7'd99)
clk_out_reg <= ~clk_out_reg;
else
clk_out_reg <= clk_out_reg;
end
assign clk_out = clk_out_reg;
endmodule
仿真激励文件
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "08/04/2019 18:04:20"
// Verilog Test Bench template for design : clk_out_test
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ps/ 1 ps
module clk_out_test_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg i_clk;
reg i_rst_n;
// wires
wire clk_out;
// assign statements (if any)
clk_out_test i1 (
// port map - connection between master ports and signals/registers
.clk_out(clk_out),
.i_clk(i_clk),
.i_rst_n(i_rst_n)
);
initial
begin
i_clk = 0;
i_rst_n = 0;
#100
i_rst_n = 1'b1;
end
always #10 i_clk = ~i_clk;
endmodule
打开modelsim
New-->Project
填写工程名,以及modelsim存储路径,其它都可以选择默认的,点击OK
点击这个添加我们上面提供的.v文件和激励文件.vt文件
选择.v文件,点击打开
点击OK
再次点击Add Existing File添加.vt激励文件
点击打开
点击OK
.v文件和.vt文件都添加进来了,点击Close,关闭Add items to the project对话框(如果.v和.vt文件
在一个地方可以一次将两个文件都添加进来)
可以从上图看到.v和vt文件都是打问号的,所以需要重新编译一次
点击Compile-->Compile All(进行全编译)
编译成功,.v和.vt文件都没有报错
切换到Library 选项卡
打开work库,这个是我们新建的库,可以看到我们添加进去的.v和.vt文件
右击这个激励文件.vt文件选择Simulate
右击这个.vt文件选择Add to -->Wave-> All items in region
我这里设置仿真时间100us,设置时间太长有时容易卡,这个仿真比较简单所以设置得比较小
选择Simulate-->Run-->Run All
点击箭头处进行全屏显示
全屏的仿真结果和程序的效果是一样的