7nm A53项目前期准备和用full netlist 做顶层规划

一、commom setting 脚本

### top design name
set design "CORTEXA53"

### design data directory
set data_dir "./data"

### gate level netlist
set import_netlists_stub "data/${design}.stub.vnet.gz"
set import_netlists_full "data/${design}.vnet.gz"

### top floorplan def
set top_floorplan_def "data/${design}.floorplan.def.gz"

### UPF
set golden_upf ""

### tech file
set synopsys_tech_tf "/data/proj/library/finfet07/v1.0/tech/PRTF_ICC2_7nm_001_Syn_V13_1a/PR_tech/Synopsys/TechFile/Standard/VHV/PRTF_ICC2_N7_15M_1X1Xa1Ya5Y2Yy2Yx2R_UTRDL_M1P57_M2P40_M3P44_M4P80_M5P76_M6P80_M7P76_M8P80_M9P76_H240.13_1a.tf"

### ndm_files 
set ndm_files ""
lappend ndm_files "/data/proj/library/finfet07/v1.0/stdcell/ndm/ts07nxpllogl08hdl057f_frame_lvf_group.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/stdcell/ndm/ts07nxpvlogl08hdl057f_frame_lvf_group.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/stdcell/ndm/ts07nxpllogl08hdh057f_frame_lvf_group.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/3rdparty/ndm/DTCD.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_128x38M4WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_1024x37M4WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_1024x32M4WM1_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/SRAMHDE_PG_SVT_16384x36M16WM0_SASS_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_128x59M4WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_128x50M2WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_160x118M2WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_256x12M4WM1_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_128x32M2WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_1024x39M4WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_256x32M4WM0_frame_ccs.ndm"
lappend ndm_files "/data/proj/library/finfet07/v1.0/sram/ndm/RFHSD_PG_SVT_2048x21M8WM1_frame_ccs.ndm"

二、使用full netlist 做顶层规划

1、步骤总结

（1）improt full netlist

（2）define top floorplan (manual)

（3）create tracks
source/disk/hd01/data/eda/cdf/20210725_v002.019/projects/finfet07/GPU/floorplan/icc2_create_tracks.tcl

（4）commit block (script)

（5）define block floorplan (shape, pin location)

（6）timing constraint (budget flow, optional)

（6）split upf

（7）write data (block & top def, netlist)

2.主要步骤

（1）improt full netlist

执行import 脚本

source scripts/00_common_initial_settings.tcl

source scripts/initialize_icc2.tcl

### variables
set current_step "01_top_import_full"

#### add block full nlib
#lappend ndm_files "data/blocks/ca53_cpu_full.nlib"
#lappend ndm_files "data/blocks/ca53_l2_full.nlib"

### add block netlists
lappend import_netlists_full "data/blocks/ca53_cpu.vnet.gz"

### create nlib
set nlib_dir "data"
file mkdir $nlib_dir
set top_nlib "${design}_full.nlib"
file delete -force $nlib_dir/$top_nlib
create_lib -technology $synopsys_tech_tf -ref_libs $ndm_files $nlib_dir/$top_nlib
set_svf -off

### read verilog
read_verilog -library $top_nlib -design ${design} -top $design $import_netlists_full

### save design
#save_lib -all

查看设计大小：

（2）commit block 

（3）define top floorplan (manual)

尽量让利用率在50%左右

（4）create tracks
source/disk/hd01/data/eda/cdf/20210725_v002.019/projects/finfet07/GPU/floorplan/icc2_create_tracks.tcl

 （5）写出def

### write data (block & top def, netlist)
# top def (shape, block location, ports, physical only IP & hard IP)
set top_def_file "data/${design}.floorplan.def"
set target_objects ""
append_to_col target_objects [get_cells -physical_context -filter "(is_hard_macro==true||is_soft_macro==true)&&physical_status!=unplaced"]
append_to_col target_objects [get_ports * -filter "port_type!=power&&port_type!=ground"]
write_def -include {ports rows_tracks cells} -objects $target_objects -version 5.8 -compress gzip -include_tech_via_definitions $top_def_file

set sub_blocks [get_blocks -hierarchical]
#set top_stack "CORTEXA53.nlib:run_220117_211341.design"
set top_stack "CORTEXA53_full.nlib:CORTEXA53.design"
foreach_in_col _block $sub_blocks {
    set block_stack [get_att ${_block} full_name]
    set block_name [get_att ${_block} name]
    set_working_design_stack $block_stack

    set block_def_file "data/blocks/${design}.floorplan.def"
    file mkdir "data/blocks"
    set target_objects ""
    append_to_col target_objects [get_cells -physical_context -filter "(is_hard_macro==true||is_soft_macro==true)&&physical_status!=unplaced"]
    append_to_col target_objects [get_ports * -filter "port_type!=power&&port_type!=ground"]
    write_def -include {ports rows_tracks cells} -objects $target_objects -version 5.8 -compress gzip -include_tech_via_definitions $block_def_file
    set_working_design_stack $top_stack

注意：本设计用stub做顶层规划