7、BDS B1I信号跟踪通道Verilog 源码

\qquad 下面是BDS B1I信号跟踪通道的Verilog代码(下载完整的HD-GR基带模块代码):

//                              -*- Mode: Verilog -*-
// Original filename : tracking_channel.v 
// Filename          : bds_tracking_channel.v 
// Description       : Wire the correlator block together. 
//                     2 bds_carrier_mixers 
//                     1 bds_carrier_nco 
//                     1 bds_code_nco 
//                     1 bds_code_gen 
//                     1 bds_epoch_counter 
//                     6 bds_accumulators 
 
// Author            : Peter Mumford, UNSW 2005 
// Author            : Cheng Huaide, turing321.com, 2015 (BDS & 1PPS - processing upgrade)
 
/* 
	Copyright (C) 2007  Peter Mumford 
 
    This library is free software; you can redistribute it and/or 
    modify it under the terms of the GNU Lesser General Public 
    License as published by the Free Software Foundation; either 
    version 2.1 of the License, or (at your option) any later version. 
 
    This library is distributed in the hope that it will be useful, 
    but WITHOUT ANY WARRANTY; without even the implied warranty of 
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU 
    Lesser General Public License for more details. 
 
    You should have received a copy of the GNU Lesser General Public 
    License along with this library; if not, write to the Free Software 
    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA 
*/ 

`include "namuro_gnss_setup.v"
 
module bds_tracking_channel (
	clk, rstn, accum_sample_enable, 
	if_sign, if_mag, 
	pre_tic_enable, tic_enable, 
	carr_nco_fc, 
	code_nco_fc, 
	prn_key, 
	prn_key_enable, 
	code_slew, slew_enable, epoch_enable, 
	dump, 
	i_early,q_early,i_prompt,q_prompt,i_late,q_late, 
`ifdef ENABLE_CARRIER_PHASE_MEASUREMENT
	carrier_val,
`endif // ENABLE_CARRIER_PHASE_MEASUREMENT
	code_val,epoch_load,epoch,epoch_check); 
 
	input clk, rstn, accum_sample_enable, if_sign, if_mag, pre_tic_enable, tic_enable, prn_key_enable, slew_enable, epoch_enable; 
	input [28:0] carr_nco_fc; 
	input [27:0] code_nco_fc; 
	input [10:0] prn_key; 
	input [11:0] code_slew; 
	input [10:0] epoch_load; 

`ifdef ENABLE_32BIT_ACCUMULATOR
	output [31:0] i_early,q_early,i_prompt,q_prompt,i_late,q_late; 
`else
	output [15:0] i_early,q_early,i_prompt,q_prompt,i_late,q_late; 
`endif
`ifdef ENABLE_CARRIER_PHASE_MEASUREMENT
	output [31:0] carrier_val; 
`endif // ENABLE_CARRIER_PHASE_MEASUREMENT
	output [10:0] epoch, epoch_check; 
	output [22:0] code_val; 
	output dump; // pulse generated (from code_gen) at the begining/end of the prompt C/A code cycle 

	wire carrier_i_sign, carrier_q_sign; 
	wire carrier_i_mag, carrier_q_mag; 
	wire mix_i_sign, mix_q_sign; 
	wire [2:0] mix_i_mag, mix_q_mag; 
	wire hc_enable, dump_enable; 
	wire early_code, prompt_code, late_code; 

	assign dump = dump_enable; 
    
	// carrier mixers ----------------------------------------------------------- 
	bds_carrier_mixer i_cos (
		.if_sign(if_sign), .if_mag(if_mag), // raw data input 
		.carrier_sign(carrier_i_sign), .carrier_mag(carrier_i_mag), // carrier nco inputs 
		.mix_sign(mix_i_sign), .mix_mag(mix_i_mag) // outputs 
		); 
	bds_carrier_mixer q_sin (
		.if_sign(if_sign), .if_mag(if_mag), // raw data input 
		.carrier_sign(carrier_q_sign), .carrier_mag(carrier_q_mag), // carrier nco inputs 
		.mix_sign(mix_q_sign), .mix_mag(mix_q_mag) // outputs 
		); 
	// carrier nco -------------------------------------------------------------- 
	bds_carrier_nco carrnco (
		.clk(clk), .rstn(rstn), 
		.f_control(carr_nco_fc), 
		
`ifdef ENABLE_CARRIER_PHASE_MEASUREMENT
		.tic_enable(tic_enable), 
		.carrier_val(carrier_val), 
`endif // ENABLE_CARRIER_PHASE_MEASUREMENT

		.i_sign(carrier_i_sign), .i_mag(carrier_i_mag), 
		.q_sign(carrier_q_sign), .q_mag(carrier_q_mag) 
		); 

	// code nco ----------------------------------------------------------------- 
	bds_code_nco codenco (
		.clk(clk), .rstn(rstn), .tic_enable(pre_tic_enable), 
		.f_control(code_nco_fc), 
		.hc_enable(hc_enable), .code_nco_phase(code_val[10:0]) 
		); 
	// code gen ----------------------------------------------------------------- 
	bds_code_gen codegen (
		.clk(clk), .rstn(rstn), .tic_enable(tic_enable), 
		.hc_enable(hc_enable), .prn_key_enable(prn_key_enable), 
		.prn_key(prn_key), .code_slew(code_slew), .slew_enable(slew_enable), 
		.dump_enable(dump_enable), .code_phase(code_val[22:11]), 
		.early(early_code), .prompt(prompt_code), .late(late_code) 
		); 

	// epoch counter ------------------------------------------------------------ 
	bds_epoch_counter epc (
		.clk(clk), .rstn(rstn), 
		.tic_enable(tic_enable), .dump_enable(dump_enable), 
		.epoch_enable(epoch_enable), .epoch_load(epoch_load), 
		.epoch(epoch), .epoch_check(epoch_check) 
		); 

	// accumulators ------------------------------------------------------------- 
	// in-phase early 
	bds_accumulator ie (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(early_code), 
		.carrier_mix_sign(mix_i_sign), .carrier_mix_mag(mix_i_mag), 
		.dump_enable(dump_enable), .accumulation(i_early) 
		); 
	// in-phase prompt 
	bds_accumulator ip (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(prompt_code), 
		.carrier_mix_sign(mix_i_sign), .carrier_mix_mag(mix_i_mag), 
		.dump_enable(dump_enable), .accumulation(i_prompt) 
		); 
	// in-phase late 
	bds_accumulator il (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(late_code), 
		.carrier_mix_sign(mix_i_sign), .carrier_mix_mag(mix_i_mag), 
		.dump_enable(dump_enable), .accumulation(i_late) 
		); 
	// quadrature-phase early 
	bds_accumulator qe (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(early_code), 
		.carrier_mix_sign(mix_q_sign), .carrier_mix_mag(mix_q_mag), 
		.dump_enable(dump_enable), .accumulation(q_early) 
		); 
	// quadrature-phase prompt 
	bds_accumulator qp (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(prompt_code), 
		.carrier_mix_sign(mix_q_sign), .carrier_mix_mag(mix_q_mag), 
		.dump_enable(dump_enable), .accumulation(q_prompt) 
		); 
	// quadrature-phase late 
	bds_accumulator ql (
		.clk(clk), .rstn(rstn), .sample_enable(accum_sample_enable), .code(late_code), 
		.carrier_mix_sign(mix_q_sign), .carrier_mix_mag(mix_q_mag), 
		.dump_enable(dump_enable), .accumulation(q_late) 
		); 
   //------------------------------------------------------------------------- 
endmodule // bds_tracking_channel 

odule GPS ( //////////////////// Clock Input //////////////////// CLOCK_24, // 24 MHz CLOCK_27, // 27 MHz CLOCK_50, // 50 MHz EXT_CLOCK, // External Clock //////////////////// Push Button //////////////////// KEY, // Pushbutton[3:0] //////////////////// DPDT Switch //////////////////// SW, // Toggle Switch[9:0] //////////////////// 7-SEG Dispaly //////////////////// HEX0, // Seven Segment Digit 0 HEX1, // Seven Segment Digit 1 HEX2, // Seven Segment Digit 2 HEX3, // Seven Segment Digit 3 //////////////////////// LED //////////////////////// LEDG, // LED Green[7:0] LEDR, // LED Red[9:0] //////////////////////// UART //////////////////////// UART_TXD, // UART Transmitter UART_RXD, // UART Receiver ///////////////////// SDRAM Interface //////////////// DRAM_DQ, // SDRAM Data bus 16 Bits DRAM_ADDR, // SDRAM Address bus 12 Bits DRAM_LDQM, // SDRAM Low-byte Data Mask DRAM_UDQM, // SDRAM High-byte Data Mask DRAM_WE_N, // SDRAM Write Enable DRAM_CAS_N, // SDRAM Column Address Strobe DRAM_RAS_N, // SDRAM Row Address Strobe DRAM_CS_N, // SDRAM Chip Select DRAM_BA_0, // SDRAM Bank Address 0 DRAM_BA_1, // SDRAM Bank Address 0 DRAM_CLK, // SDRAM Clock DRAM_CKE, // SDRAM Clock Enable //////////////////// Flash Interface //////////////// FL_DQ, // FLASH Data bus 8 Bits FL_ADDR, // FLASH Address bus 22 Bits FL_WE_N, // FLASH Write Enable FL_RST_N, // FLASH Reset FL_OE_N, // FLASH Output Enable FL_CE_N, // FLASH Chip Enable //////////////////// SRAM Interface //////////////// SRAM_DQ, // SRAM Data bus 16 Bits SRAM_ADDR, // SRAM Address bus 18 Bits SRAM_UB_N, // SRAM High-byte Data Mask SRAM_LB_N, // SRAM Low-byte Data Mask SRAM_WE_N, // SRAM Write Enable SRAM_CE_N, // SRAM Chip Enable SRAM_OE_N, // SRAM Output Enable //////////////////// SD_Card Interface //////////////// SD_DAT, // SD Card Data SD_DAT3, // SD Card Data 3 SD_CMD, // SD Card Command Signal SD_CLK, // SD Card Clock //////////////////// USB JTAG link //////////////////// TDI, // CPLD -> FPGA (data in) TCK, // CPLD -> FPGA (clk) TCS, // CPLD -> FPGA (CS) TDO, // FPGA -> CPLD (data out) //////////////////// I2C //////////////////////////// I2C_SDAT, // I2C Data I2C_SCLK, // I2C Clock //////////////////// PS2 //////////////////////////// PS2_DAT, // PS2 Data PS2_CLK, // PS2 Clock //////////////////// VGA //////////////////////////// VGA_HS, // VGA H_SYNC
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