vivado2020.1 HLS生成的IP在Windows下报错
Frambuffer_rd在Windows下的vivado 2020.1编译报错解决方法
解决方法参考Xilinx官方论坛的解决方法，帖子链接如下：
https://forums.xilinx.com/t5/Vivado/Synth-8-439-module-not-found-%E7%BB%BC%E5%90%88%E5%9F%BA%E4%BA%8EHLS%E7%9A%84IP%E5%A4%B1%E8%B4%A5/m-p/1031081
If you are unsure which, if any, IP cores in the project are HLS based, you can also just run compile_c on all of the IP
(foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj}).
用这个命令foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}看会不会报错。
我的解决方法：
我所报的错如下：
ERROR: [Synth 8-439] module ‘bd_v_frmbuf_rd_0_1_v_frmbuf_rd’ not found [f:/test/rdf0428-zcu106-vcu-t。。。。
在tcl框下输入如下命令，对工程内所有的基于hls的IP进行重新编译
foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}
编译过程如下
foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}
****** Vivado™ HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source E:/program_install/Vivado/2020.1/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running ‘E:/program_install/Vivado/2020.1/bin/unwrapped/win64.o/vivado_hls.exe’
INFO: [HLS 200-10] For user ‘Think’ on host ‘desktop-ka8h0t3’ (Windows NT_amd64 version 6.2) on Wed May 19 19:55:05 +0800 2021
INFO: [HLS 200-10] In directory ‘C:/Users/Think/AppData/Roaming/Xilinx/Vivado’
Sourcing Tcl script ‘c:/Users/Think/AppData/Roaming/Xilinx/Vivado/runhls.tcl’
INFO: [HLS 200-10] Creating and opening project ‘C:/Users/Think/AppData/Roaming/Xilinx/Vivado/bd_v_frmbuf_rd_0_1’.
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/v_frmbuf_rd_config.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/v_frmbuf_rd.cpp’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/v_frmbuf_rd.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls_video.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls_opencv.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_axi_io.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_arithm.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_core.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_fast.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_haar.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_harris.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_histogram.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_hough.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_imgbase.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_imgproc.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_io.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_mem.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_stereobm.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_types.h’ to the project
INFO: [HLS 200-10] Adding design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/hls/hls_video_undistort.h’ to the project
INFO: [HLS 200-10] Creating and opening solution ‘C:/Users/Think/AppData/Roaming/Xilinx/Vivado/bd_v_frmbuf_rd_0_1/prj’.
INFO: [HLS 200-10] Setting target device to ‘xczu7ev-ffvc1156-2-e’
INFO: [SYN 201-201] Setting up clock ‘ap_clk’ with a period of 3.333ns.
INFO: [SCHED 204-61] Option ‘relax_ii_for_timing’ is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file ‘f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/v_frmbuf_rd.cpp’ …
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:03 ; elapsed = 00:00:47 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:03 ; elapsed = 00:00:47 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [HLS 200-10] Starting code transformations …
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:05 ; elapsed = 00:00:50 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [HLS 200-10] Checking synthesizability …
WARNING: [SYNCHK 200-23] f:/test/rdf0428-zcu106-vcu-trd-2020-1/rdf0428-zcu106-vcu-trd-2020.1/pl/prj/build/zcu106_hdmitx/zcu106_hdmitx.srcs/sources_1/bd/bd/ip/bd_v_frmbuf_rd_0_1/src/v_frmbuf_rd.cpp:248: variable-indexed range selection may cause suboptimal QoR.
INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s).
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:06 ; elapsed = 00:00:52 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-2.1’ in function ‘MultiPixStream2AXIvideo’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-1.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-2.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-3.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-4.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-5.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-6.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop ‘Loop-7.1’ in function ‘Bytes2MultiPixStream’ for pipelining.
INFO: [HLS 200-489] Unrolling loop ‘Loop-2.1.1’ in function ‘MultiPixStream2AXIvideo’ completely with a factor of 6.
INFO: [HLS 200-489] Unrolling loop ‘Loop-2.1.2’ in function ‘MultiPixStream2AXIvideo’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-2.1.2.1’ in function ‘MultiPixStream2AXIvideo’ completely with a factor of 3.
INFO: [HLS 200-489] Unrolling loop ‘Loop-1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 8.
INFO: [HLS 200-489] Unrolling loop ‘Loop-1.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-2.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 4.
INFO: [HLS 200-489] Unrolling loop ‘Loop-2.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-3.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 4.
INFO: [HLS 200-489] Unrolling loop ‘Loop-3.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-4.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 8.
INFO: [HLS 200-489] Unrolling loop ‘Loop-4.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-5.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-5.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-6.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 8.
INFO: [HLS 200-489] Unrolling loop ‘Loop-6.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-7.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [HLS 200-489] Unrolling loop ‘Loop-7.1.1.1’ in function ‘Bytes2MultiPixStream’ completely with a factor of 2.
INFO: [XFORM 203-102] Automatically partitioning streamed array ‘img.V.val.V’ .
INFO: [XFORM 203-101] Partitioning array ‘tmp.val.V’ in dimension 1 completely.
INFO: [XFORM 203-712] Applying dataflow to function ‘v_frmbuf_rd’ , detected/extracted 5 process function(s):
‘Block_.crit_edge44_proc’
‘AXIMMvideo2Bytes’
‘Bytes2MultiPixStream’
'Block.crit_edge447_proc’
‘MultiPixStream2AXIvideo’.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:11 ; elapsed = 00:00:56 . Memory (MB): peak = 973.141 ; gain = 876.832
WARNING: [XFORM 203-631] Renaming function ‘MultiPixStream2AXIvideo’ to ‘MultiPixStream2AXIvi’
WARNING: [XFORM 203-631] Renaming function 'Block.crit_edge44_proc’ to 'Block.crit_edge44’
WARNING: [XFORM 203-631] Renaming function ‘Block_.crit_edge447_proc’ to 'Block.crit_edge447’
INFO: [HLS 200-444] Inferring multiple bus burst read of variable length on port ‘srcImg.V’ with 2 times. These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings.
WARNING: [XFORM 203-631] Renaming function 'Block.crit_edge44_5’ to 'Block.crit_edge44’
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:15 ; elapsed = 00:01:00 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [HLS 200-10] Starting hardware synthesis …
INFO: [HLS 200-10] Synthesizing ‘v_frmbuf_rd’ …
WARNING: [SYN 201-103] Legalizing function name ‘Block_.crit_edge44’ to ‘Block_crit_edge44_s’.
WARNING: [SYN 201-103] Legalizing function name 'Block_.crit_edge447’ to ‘Block_crit_edge447’.
WARNING: [SYN 201-103] Legalizing function name ‘reg’ to ‘reg_unsigned_short_s’.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘Block_crit_edge44_s’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 60.681 seconds; current allocated memory: 330.168 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.364 seconds; current allocated memory: 330.312 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘AXIMMvideo2Bytes’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-61] Pipelining loop ‘loop_AXIMMvideo2Bytes_2planes.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop ‘loop_AXIMMvideo2Bytes_2planes.2’.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.733 seconds; current allocated memory: 331.132 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 3.562 seconds; current allocated memory: 332.273 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘Bytes2MultiPixStream’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-61] Pipelining loop ‘loop_BGRX8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 2, Final II = 2, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop ‘loop_Y8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 9.
INFO: [SCHED 204-61] Pipelining loop ‘loop_RGBX8_YUVX8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 2, Final II = 2, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop ‘loop_RGB8_YUV8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 9.
INFO: [SCHED 204-61] Pipelining loop ‘loop_UYVY8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 5.
INFO: [SCHED 204-61] Pipelining loop ‘loop_YUYV8.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 5.
INFO: [SCHED 204-61] Pipelining loop ‘loop_Y_UV8_Y_UV8_420.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 10.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 5.103 seconds; current allocated memory: 334.474 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 7.917 seconds; current allocated memory: 337.068 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘Block_crit_edge447’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 7.777 seconds; current allocated memory: 337.142 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.207 seconds; current allocated memory: 337.188 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘reg_unsigned_short_s’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.201 seconds; current allocated memory: 337.201 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.203 seconds; current allocated memory: 337.242 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘MultiPixStream2AXIvi’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-61] Pipelining loop ‘Loop 2.1’.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.315 seconds; current allocated memory: 337.541 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 1.255 seconds; current allocated memory: 338.022 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] – Implementing module ‘v_frmbuf_rd’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling …
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.278 seconds; current allocated memory: 338.200 MB.
INFO: [BIND 205-100] Starting micro-architecture generation …
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding …
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 1.439 seconds; current allocated memory: 338.924 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘Block_crit_edge44_s’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name ‘Block_crit_edge44_s_BYTES_PER_PIXEL’ to ‘Block_crit_edge44bkb’ due to the length limit 20
INFO: [RTGEN 206-100] Finished creating RTL model for ‘Block_crit_edge44_s’.
INFO: [HLS 200-111] Elapsed time: 1.216 seconds; current allocated memory: 339.245 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘AXIMMvideo2Bytes’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for ‘AXIMMvideo2Bytes’.
INFO: [HLS 200-111] Elapsed time: 0.532 seconds; current allocated memory: 341.630 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘Bytes2MultiPixStream’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name ‘v_frmbuf_rd_urem_13ns_3ns_2_17_seq_1’ to ‘v_frmbuf_rd_urem_cud’ due to the length limit 20
INFO: [SYN 201-210] Renamed object name ‘v_frmbuf_rd_mul_mul_15ns_13ns_28_1_1’ to ‘v_frmbuf_rd_mul_mdEe’ due to the length limit 20
INFO: [RTGEN 206-100] Generating core module ‘v_frmbuf_rd_mul_mdEe’: 1 instance(s).
INFO: [RTGEN 206-100] Generating core module ‘v_frmbuf_rd_urem_cud’: 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for ‘Bytes2MultiPixStream’.
INFO: [HLS 200-111] Elapsed time: 3.942 seconds; current allocated memory: 346.048 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘Block_crit_edge447’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name ‘Block_crit_edge447_MEMORY2LIVE’ to ‘Block_crit_edge44eOg’ due to the length limit 20
INFO: [RTGEN 206-100] Finished creating RTL model for ‘Block_crit_edge447’.
INFO: [HLS 200-111] Elapsed time: 8.348 seconds; current allocated memory: 346.091 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘reg_unsigned_short_s’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for ‘reg_unsigned_short_s’.
INFO: [HLS 200-111] Elapsed time: 0.263 seconds; current allocated memory: 346.203 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘MultiPixStream2AXIvi’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name ‘MultiPixStream2AXIvi_mapComp’ to ‘MultiPixStream2AXfYi’ due to the length limit 20
INFO: [SYN 201-210] Renamed object name ‘v_frmbuf_rd_mux_63_8_1_1’ to ‘v_frmbuf_rd_mux_6g8j’ due to the length limit 20
INFO: [RTGEN 206-100] Generating core module ‘v_frmbuf_rd_mux_6g8j’: 6 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for ‘MultiPixStream2AXIvi’.
INFO: [HLS 200-111] Elapsed time: 0.33 seconds; current allocated memory: 347.184 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] – Generating RTL for module ‘v_frmbuf_rd’
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/mm_video’ to ‘m_axi’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_width’ to ‘s_axilite & ap_stable’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_height’ to ‘s_axilite & ap_stable’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_stride’ to ‘s_axilite & ap_stable’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_video_format’ to ‘s_axilite & ap_stable’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_frm_buffer_V’ to ‘s_axilite & ap_none’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/HwReg_frm_buffer2_V’ to ‘s_axilite & ap_none’.
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_data_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_keep_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_strb_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_user_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_last_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_id_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port ‘v_frmbuf_rd/m_axis_video_V_dest_V’ to ‘axis’ (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on function ‘v_frmbuf_rd’ to ‘s_axilite & ap_ctrl_hs’.
INFO: [RTGEN 206-100] Bundling port ‘HwReg_width’, ‘HwReg_height’, ‘HwReg_stride’, ‘HwReg_video_format’, ‘HwReg_frm_buffer_V’, ‘HwReg_frm_buffer2_V’ and ‘return’ to AXI-Lite port CTRL.
INFO: [SYN 201-210] Renamed object name ‘start_for_Bytes2MultiPixStream_U0’ to ‘start_for_Bytes2Mhbi’ due to the length limit 20
INFO: [SYN 201-210] Renamed object name ‘start_for_MultiPixStream2AXIvi_U0’ to ‘start_for_MultiPiibs’ due to the length limit 20
INFO: [RTGEN 206-100] Finished creating RTL model for ‘v_frmbuf_rd’.
INFO: [HLS 200-111] Elapsed time: 1.48 seconds; current allocated memory: 348.634 MB.
INFO: [WVHDL 200-304] Encrypting RTL VHDL done.
INFO: [WVHDL 200-304] Encrypting RTL Verilog done.
INFO: [RTMG 210-279] Implementing memory ‘bd_v_frmbuf_rd_0_1_Block_crit_edge44bkb_rom’ using distributed ROMs.
INFO: [RTMG 210-282] Generating pipelined core: ‘bd_v_frmbuf_rd_0_1_v_frmbuf_rd_urem_cud_div’
INFO: [RTMG 210-279] Implementing memory ‘bd_v_frmbuf_rd_0_1_Block_crit_edge44eOg_rom’ using distributed ROMs.
INFO: [RTMG 210-279] Implementing memory ‘bd_v_frmbuf_rd_0_1_MultiPixStream2AXfYi_rom’ using distributed ROMs.
INFO: [RTMG 210-285] Implementing FIFO ‘mul_ln131_loc_c_U(bd_v_frmbuf_rd_0_1_fifo_w16_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘trunc_ln131_loc_c_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘HwReg_frm_buffer_V_c_U(bd_v_frmbuf_rd_0_1_fifo_w64_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘HwReg_frm_buffer2_V_s_24_U(bd_v_frmbuf_rd_0_1_fifo_w64_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘tmp_U(bd_v_frmbuf_rd_0_1_fifo_w16_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘bytePlanes_plane0_V_s_U(bd_v_frmbuf_rd_0_1_fifo_w128_d480_B)’ using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO ‘bytePlanes_plane1_V_s_U(bd_v_frmbuf_rd_0_1_fifo_w128_d480_B)’ using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO ‘mul_ln131_loc_c14_U(bd_v_frmbuf_rd_0_1_fifo_w16_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘trunc_ln131_loc_c15_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_0_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_1_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_2_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_3_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_4_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘img_V_val_5_V_U(bd_v_frmbuf_rd_0_1_fifo_w8_d2_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘trunc_ln139_loc_c_U(bd_v_frmbuf_rd_0_1_fifo_w3_d3_A)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘start_for_Bytes2Mhbi_U(bd_v_frmbuf_rd_0_1_start_for_Bytes2Mhbi)’ using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO ‘start_for_MultiPiibs_U(bd_v_frmbuf_rd_0_1_start_for_MultiPiibs)’ using Shift Registers.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:01:02 ; elapsed = 00:02:00 . Memory (MB): peak = 973.141 ; gain = 876.832
INFO: [VHDL 208-304] Generating VHDL RTL for v_frmbuf_rd with prefix bd_v_frmbuf_rd_0_1.
INFO: [VLOG 209-307] Generating Verilog RTL for v_frmbuf_rd with prefix bd_v_frmbuf_rd_0_1_.
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.
****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository ‘E:/program_install/Vivado/2020.1/data/ip’.
INFO: [Common 17-206] Exiting Vivado at Wed May 19 19:57:28 2021…
INFO: [HLS 200-112] Total elapsed time: 144.787 seconds; peak allocated memory: 348.634 MB.
INFO: [Common 17-206] Exiting vivado_hls at Wed May 19 19:57:29 2021…
compile_c: Time (s): cpu = 00:00:06 ; elapsed = 00:02:30 . Memory (MB): peak = 2687.809 ; gain = 0.000
Converted RTL already exists. Skipping compile_c
之后重新对工程generate ，这样就可以了。
也可以单独对IP进行编译（没试过）
compile_c [get_ips tl_cameralink_display_v_demosaic_0_0]
compile_c [get_ips tl_cameralink_display_v_mix_0_0]
另外一种笨方法
Linux环境下的vivado 可以正常编译基于hls的IP
565
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