xilinx LVDS使用注意事项

参考 《selectio_wiz_gsg700》https://china.xilinx.com/support/documentation/ip_documentation/selectio_wiz/v4_1/selectio_wiz_gsg700.pdf

由于V4.1版本IP中串化模块最高只支持8位并转串，所以当并口为16位只能自己提前转好，

由于要输出4KP30视频，则时钟采用297M，输出为8条LVDS数据线，所以需要用到DDR

 

通过提示我们知道要采用DDR那么输入时钟这里需要用两个BUFIO2，所以我们就先选用BUFG

 

 

速率特性

artix-7

Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Artix-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 11.
Table 15: Networking Applications Interface Performances
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.

 

Spartan-6

This section provides the performance characteristics of some common functions and designs implemented in
Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values
are subject to the same guidelines as the Switching Characteristics, page 19.
Table 25: Interface Performances