有时候写个小工程测试综合频率,但会出现<No paths to report.>,因为是组合逻辑,首先组合逻辑没有时钟;如果想测看该组合逻辑的频率,只能另写一带时钟的顶层模块,输入输出都加一级寄存器,下面实现一比较器:因为CASU本身是组合逻辑,不可能综合出时钟频率,只能另加top.v,这样既可综合出频率
CASU.v
//***********************************************
// DEFINE MODULE PORT //
//***********************************************
module CASU(//input
in1,
in2,
//output
max,
min);
//*******************************************
// DEFINE INPUT
//*******************************************
input [9:0] in1;
input [9:0] in2;
//*******************************************
// DEFINE OUTPUT
//*******************************************
output [9:0] min;
output [9:0] max;
//*********************************************
//MAIN CODE
//********************************************
assign max = (in1 <= in2) ? in2 : in1;
assign min = (in1 > in2) ? in2 : in1;
//*********************************************
endmodule
//*********************************************
/*********************top.v*******************/
module top(//input
clk,
in1,
in2,
//output
out1,
out2
);
input clk;
input [9:0] in1;
input [9:0] in2;
output reg [9:0] out1;
output reg [9:0] out2;
reg [9:0] rin1;
reg [9:0] rin2;
wire [9:0] wout1;
wire [9:0] wout2;
always @(posedge clk)
begin
rin1 <= in1;
rin2 <= in2;
end
always @(posedge clk)
begin
out1 <= wout1;
out2 <= wout2;
end
CASU CASU_inst(
.in1(rin1),
.in2(rin2),
.min(wout1),
.max(wout2)
);
endmodule
框图如下: