HDLbits.1

Exams/2013 q2bfsm

//A0->A1->B0->B1->B2->C->(D, E->(D,F))

 

                                        

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
);
    parameter A0=0,A1=1,B0=2,B1=3,B2=4,C=5,D=6,E=7,F=8;
    reg[3:0]state,nstate;
    always@(posedge clk)begin
        if(~resetn)state<=A0;
        else state<=nstate;
    end
    always@(*)begin
        case(state)
            A0:begin
                nstate=A1;
            end
            A1:begin
                nstate=B0;
            end
            B0:begin
                if(x)nstate=B1;
                else nstate=B0;
            end
            B1:begin
                if(x)nstate=B1;
                else nstate=B2;
            end
            B2:begin
                if(x)nstate=C;
                else nstate=B0;
            end
            C:begin
                if(y) nstate=D;
                else nstate=E;
            end
            D:begin
                nstate=D;
            end
            E:begin
                if(y) nstate=D;
                else nstate=F;
            end
            F:begin
                nstate=F;
            end
            default:nstate=A0;
        endcase
    end
    assign f=state==A1;
    assign g=state==C|state==D|state==E;
endmodule