module top_module (
input [6:1] y,
input w,
output Y2,
output Y4);
parameter A = 6'b000001;
parameter B = 6'b000010;
parameter C = 6'b000100;
parameter D = 6'b001000;
parameter E = 6'b010000;
parameter F = 6'b100000;
reg [6:1] next;
assign next[1] = y[4]&(w)|y[1]&(w);
assign next[2] = y[1]&(~w);
assign next[3] = y[2]&(~w)|y[6]&(~w);
assign next[4] = y[2]&(w)|y[3]&(w)|y[5]&(w)|y[6]&(w);
assign next[5] = y[5]&(~w)|y[3]&(~w);
assign next[6] = y[4]&(~w);
assign Y2 = next[2];
assign Y4 = next[4];
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q6c: FSM one-hot next-state logic
最新推荐文章于 2024-09-20 18:58:38 发布