module async_handshake(
input clk0,
input clk1,
input rst0_n,
input rst1_n,
input req_i,
output ack_o,
output req_o
);
// clk0
reg req_i_1ff;
always @(posedge clk0, negedge rst0_n)begin
if(~rst0_n)begin
req_i_1ff <= 1'b0;
end
else begin
req_i_1ff <= req_i;
end
end
//clk1
reg req_sync_1ff,req_sync_2ff,req_sync_3ff;
always @(posedge clk1, negedge rst1_n)begin
if(~rst1_n)begin
{req_sync_1ff,req_sync_2ff,req_sync_3ff} <= 3'b0;
end
else begin
{req_sync_1ff,req_sync_2ff,req_sync_3ff} <= {req_i_1ff,req_sync_1ff,req_sync_2ff};
end
en