Xilinx FPGA 10G Ethernet Subsystem example

The 10G Ethernet subsystem provides 10 Gb/s Ethernet MAC, Physical Coding Sublayer(PCS) and Physical Medium Attachment (PMA) transmit and receive functionality over an AXI4-Stream interface. The subsystem is designed to interface with a 10GBASE-R Physical-Side Interface (PHY) or a 10GBASE-KR backplane and is designed to the IEEE Standard 802.3-2012, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications (IEEE Std 802.3).

Figure 1-1 shows a typical Ethernet system architecture and the subsystem within it. The MAC and all the blocks to the right are defined in IEEE Std 802.3 [Ref pg157-axi-10g-ethernet].

Figure 1-1: Typical Ethernet System Architecture

The subsystem also provides an optional high accuracy timestamping capability compatible with IEEE Std 1588-2008 (also known as IEEE1588v2). This is available for the 10GBASE-R standard. Figure 1-1 shows the block diagram of the 10G Ethernet MAC subsystem.

Figure 1-2: 10 Gigabit Ethernet High-Level Block Diagram

Figure 1-3 illustrates the relationship between the Open Systems Interconnection (OSI) reference model and the core. The grayed-in layers show the functionality that the core handles. Figure 1-3 also shows where the supported physical interfaces fit into the architecture.

Figure 1-3: IEEE Std 802.3-2012 Ethernet Model

Physical Coding Sublayer(PCS), coding the data stream from MAC.

Physical Medium Attachment(PMA), which is responsible for transmit/receive, serial parallel conversion.

Physical medium dependent(PMD) sublayers define the d