■ Core: ARM 32-bit Cortex™-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 168 MHz,
memory protection unit,210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
SOC端 控制器(SPI)
SPI接口
2.2.23 Serial peripheral interface (SPI)
The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and
simplex communication modes. SPI1 can communicate at up to 37.5 Mbits/s, SPI2 and
SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
Figure 39. SPI timing diagram - master mode
寄存器
- 正点原子探索者开发板 STM32407ZET6 cortex-M4 -外扩 W25Q128:16M,NorFlash,SPI接口soc■ Core: ARM 32-bit Cortex™-M4 CPU with FPU,Adaptive real-time accelerator (ARTAccelerator™) allowing 0-wait state executi...