VHDL 七段显示译码器

最新推荐文章于 2024-09-18 13:54:39 发布

csyzcyj

最新推荐文章于 2024-09-18 13:54:39 发布

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分类专栏：硬件文章标签： VHDL 显示译码器 Quartus

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使用Quartus Ⅱ，器件为MAXⅡ——EPM240T100C5

七段显示译码器VHDL语言的代码如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
Entity seg7_4 is --工程名为seg7_4
       PORT ( BCD_in  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);   --输入四位BCD码
               SG_out  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));  --输出七位字形码
 END;
ARCHITECTURE one OF seg7_4 IS
       BEGIN
        PROCESS(BCD_in)
          BEGIN
           CASE  BCD_in  IS
            WHEN "0000"  => SG_out <= "0111111";  
            WHEN "0001"  => SG_out <= "0000110"; 
            WHEN "0010"  => SG_out <= "1011011"; 
            WHEN "0011"  => SG_out <= "1001111"; 
            WHEN "0100"  => SG_out <= "1100110";  
            WHEN "0101"  => SG_out <= "1101101"; 
            WHEN "0110"  => SG_out <= "1111101"; 
            WHEN "0111"  => SG_out <= "0000111";
            WHEN "1000"  => SG_out <= "1111111";  
            WHEN "1001"  => SG_out <= "1101111"; 
            WHEN "1010" => SG_out <= "1110111";  
            WHEN "1011" => SG_out <= "1111100";
            WHEN "1100" => SG_out <= "0111001"; 
            WHEN "1101" => SG_out <= "1011110"; 
            WHEN "1110" => SG_out <= "1111001";  
            WHEN "1111" => SG_out <= "1110001";
            WHEN OTHERS =>  NULL ;
           END CASE ;
          END PROCESS;    
END;

注意仔细对应SG_out和BCD_in的管脚

编译并下载后，更改BCD_in四个管脚对应的电平，即可显示出0~9、A~F这十六种字符

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