HDLbits--Fsm1/Fsm1s

参考有限状态机

1.定义状态，定义状态寄存器（state，nextstate）

2.定义组合逻辑--状态转换逻辑

3.定义时序逻辑--何时转换状态/ 描述输出？

4.定义输出--应该可以放在3中？

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        state<=next_state;
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            next_state<=B;
        else
        case(state)
            A:begin
                if(in)
                    begin
                        next_state<=A;
                    end
                else
                    begin
                        next_state<=B;
                    end
            end
            B:begin
                if(in)
                    begin
                        next_state<=B;
                    end
                else
                    begin
                        next_state<=A;
                    end
            end
        endcase
                    
            
        
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state==A)?0:1;

endmodule

参考答案： 

一个状态机主要要包括三个部分

1.状态转换逻辑（组合逻辑）

2.状态触发（时序逻辑）

3.输出逻辑（组合逻辑）

module top_module (
	input clk,
	input in,
	input areset,
	output out
);

	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	parameter A=0, B=1;
	reg state;		// Ensure state and next are big enough to hold the state encoding.
	reg next;
    
    
    // A finite state machine is usually coded in three parts:
    //   State transition logic
    //   State flip-flops
    //   Output logic
    // It is sometimes possible to combine one or more of these blobs of code
    // together, but be careful: Some blobs are combinational circuits, while some
    // are clocked (DFFs).
    
    
    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.
    always@(*) begin
		case (state)
			A: next = in ? A : B;
			B: next = in ? B : A;
		endcase
    end
    
    
    
    // Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
    always @(posedge clk, posedge areset) begin
		if (areset) state <= B;		// Reset to state B
        else state <= next;			// Otherwise, cause the state to transition
	end
		
		
		
	// Combinational output logic. In this problem, an assign statement is the simplest.
	// In more complex circuits, a combinational always block may be more suitable.
	assign out = (state==B);

	
endmodule

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A = 0,B = 1;

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            next_state=B;
        end else begin
            case (present_state)
                // Fill in state transition logic
                A:
                    next_state=in?A:B;
                B:
                    next_state=in?B:A;
                        
            endcase
        end

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                // Fill in output logic
                A:
                    out=1'b0;
                B:
                    out=1'b1;
            endcase
        //end
    end

endmodule

没搞懂的：end的位置？阻塞赋值？