【FPGA】【Verilog】【基础模块】分频器

1/2分频，借助always 的敏感表实现：

	module half_clk(reset, clk_in,clk_out);
	input clk_in, reset;
	output clk_out;
	reg clk_out;
	
	always @(posedge clk_in)
	begin
	if (!reset)
		clk_out = 0;
	else 
		clk_out = !clk_out;
	end 
endmodule 

       testbench:

`timescale 1ns/100ps
`define clk_cycle 50
module halfclktest;
reg clk_in,reset;
wire clk_out;
always #`clk_cycle clk_in = ~clk_in;
initial
 begin
 clk_in = 0;
 reset = 1;
 #100 reset = 0;
 #100 reset = 1;
 #10000 $stop;
 end
half_clk half_clk(.reset(reset),.clk_in(clk_in),.clk_out(clk_out)) ;
endmodule

1/4分频，借助计数器实现：

module fdivision(reset,f10m,f500k);
	input f10m,reset;
	output f500k;
	reg f500k;
	reg [7:0] j;
		always @(posedge f10m )
			if (!reset)
				begin 
					f500k <= 0 ;
					j <= 0;
				end
			else