pll的设定:
例化:
`timescale 1 ns / 1 ps
module pll_test(
input clk,
input rst_n,
output clk1,
output clk2,
output clk3,
output clk4,
output locked
);
pll_rty pll(
.areset(rst_n),
.inclk0(clk),
.c0(clk1),
.c1(clk2),
.c2(clk3),
.c3(clk4),
.locked(locked)
);
endmodule
Testbench:
`timescale 1 ns/ 1 ps
module pll_test_vlg_tst();
reg clk;
reg rst_n;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
wire locked ;
// assign statements (if any)
pll_test i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.clk1(clk1),
.clk2(clk2),
.clk3(clk3),
.clk4(clk4),
.rst_n(rst_n),
.locked(locked)
);
initial
begin
clk = 0;
rst_n = 0;
//locked = 1;
#2000
rst_n = 1;
#500
rst_n = 0;
//locked = 0;
#1000
#100 $stop;
end
always #10 clk = ~clk;
endmodule
仿真时序: