【FPGA】【Verilog】【基础模块】8-3编码器

使用for实现：

module encoder1(none_on,out ,in);
	output none_on;
	output [2:0] out;
	input [7:0] in;
	
	reg [2:0] out;
	reg none_on;
	
	always @(in)
		begin 
	 integer i;
			out = 0;
			none_on = 1;
			
			for (i = 0;i<8 ; i = i+1)
				begin 
					if(in[i])
						begin 
						out = i;
						none_on = 0;
						end
				end
		end
	endmodule 

使用()？():()实现：

module encoder2(none_on,out2,out1,out0,h,g,f,e,d,c,b,a);
	input h,g,f,e,d,c,b,a;
	output none_on,out2,out1,out0 ;
	wire [3:0] outvec;
	
	assign outvec =  h? 4'b0111: 
											g? 4'b0110:
															f? 4'b0101:
																			e?4'b0100:
																						 d?4'b0011:
																										c?4'b0010:
																													 b?4'b0001:
																																	a?4'b0000:	
																																				 4'b1000;
																																				 
	assign none_on = outvec[3];
	assign out2 = outvec[2];
	assign out1 = outvec[1];
	assign out0 = outvec[0];
	
endmodule 
	

使用if else实现：

module  encoder3(none_on,out2,out1,out0,h,g,f,e,d,c,b,a);
	input h,g,f,e,d,c,b,a;
	output none_on,out2,out1,out0;
	reg [3:0] outvec;
	
always @(a or b or c or d or e or f or g or h)
	begin 
		if(h) 		outvec = 4'b0111;
		else if(a) 	outvec = 4'b0000;
		else if(b) 	outvec = 4'b0001;
		else if(c) 	outvec = 4'b0010;
		else if(d) 	outvec = 4'b0011;
		else if(e) 	outvec = 4'b0100;
		else if(f) 	outvec = 4'b0101;
		else if(g) 	outvec = 4'b0110;
		else outvec = 4'b1000;
	end
	
assign {none_on,out2,out1,out0} = outvec;
endmodule