CLB Overview

总结：

不同系列片子的逻辑单元CLB以及包含的slice的结构不同，具体例如为构成slice的LUT和FF--触发器的比例不同。详情如下：

                                                    UltraScale Architecture Configurable Logic Block

Chapter 2

CLB Functionality
Overview
This chapter provides a detailed view of the UltraScale™ architecture CLB. These details are
useful for design optimization and verification, but are not necessary for initiating a design.
This chapter includes:
• CLB Resources: An overview of CLB slice features.
• Look-Up Table: A description of the logical function generators.
• Storage Elements: A description of and controls for the latches and flip-flops.
• Multiplexers: Dedicated gates for combining LUTs into wide functions.
• Carry Logic: Dedicated gates and cascading to implement efficient arithmetic functions.
• Distributed RAM (SLICEM Only): Using the SLICEM LUTs as writable memory.
• Shift Registers (SLICEM Only): Using the SLICEM LUTs as shift registers.
CLB Resources
Every CLB contains one slice with eight 6-input LUTs and sixteen storage elements. The LUTs
are organized as a column with an 8-bit carry chain per CLB, called CARRY8. Wide-function
multiplexers combine LUTs to create any function of 7, 8, or 9 inputs, or some functions of
up to 55 inputs. SLICEL is the name used to describe CLB slices that support these functions,
where the L is for logic. The LUT in a SLICEM, where the M is for memory, can be configured
as a look-up table, 64-bit distributed RAM, or a 32-bit shift register. The CLB for a SLICEL is
referred to as a CLEL tile, and the CLB for the SLICEM is referred to as a CLE_M tile. Table 2-1
summarizes the resources in one CLB.

Table 2-1: Logic Resources in One CLB Slice

                                             7 Series FPGAs Configurable Logic Block

CLB Slices
A CLB element contains a pair of slices, and each slice is composed of four 6-input LUTs
and eight storage elements.
• SLICE(0) – slice at the bottom of the CLB and in the left column
• SLICE(1) – slice at the top of the CLB and in the right column
These two slices do not have direct connections to each other, and each slice is organized as
a column. Each slice in a column has an independent carry chain.

The Xilinx tools designate slices with these definitions:
• An “X” followed by a number identifies the position of each slice in a pair as well as
the column position of the slice. The “X” number counts slices starting from the
bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc.
• A “Y” followed by a number identifies a row of slices. The number remains the same
within a CLB, but counts up in sequence from one CLB row to the next CLB row,
starting from the bottom.

Figure 2-2 shows four CLBs located in the bottom-left corner of the die.

CLB/Slice Configurations

Table 2-1 summarizes the logic resources in one CLB. Each SLICEM LUT can be configured
as a look-up table, distributed RAM, or a shift register.

Table 2-1: Logic Resources in One CLB

Slice Description
Every slice contains:
• Four logic-function generators (or look-up tables)
• Eight storage elements
• Wide-function multiplexers
• Carry logic
These elements are used by all slices to provide logic, arithmetic, and ROM functions. In
addition, some slices support two additional functions: storing data using distributed
RAM and shifting data with 32-bit registers. Slices that support these additional functions
are called SLICEM; others are called SLICEL. SLICEM (shown in Figure 2-3) represents a
superset of elements and connections found in all slices. SLICEL is shown in Figure 2-4.
Each CLB can contain two SLICEL or a SLICEL and a SLICEM.